/[gxemul]/trunk/src/include/mb86960reg.h
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Contents of /trunk/src/include/mb86960reg.h

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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 13438 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============
1 /* GXemul: $Id: mb86960reg.h,v 1.1 2006/11/06 05:32:38 debug Exp $ */
2 /* $NetBSD: mb86960reg.h,v 1.10 2005/12/11 12:21:27 christos Exp $ */
3
4 #ifndef MB86960REG_H
5 #define MB86960REG_H
6
7 #define MB8696X_NREGS 32
8
9 /*
10 * All Rights Reserved, Copyright (C) Fujitsu Limited 1995
11 *
12 * This software may be used, modified, copied, distributed, and sold, in
13 * both source and binary form provided that the above copyright, these
14 * terms and the following disclaimer are retained. The name of the author
15 * and/or the contributor may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /*
32 * Registers of Fujitsu MB86960A/MB86965A Ethernet controller.
33 * Written and contributed by M.S. <seki@sysrap.cs.fujitsu.co.jp>
34 */
35
36 /*
37 * Notes on register naming:
38 *
39 * Fujitsu documents for MB86960A/MB86965A use no mnemonic names
40 * for their registers. They defined only three names for 32
41 * registers and appended numbers to distinguish registers of
42 * same name. Surprisingly, the numbers represent I/O address
43 * offsets of the registers from the base addresses, and their
44 * names correspond to the "bank" the registers are allocated.
45 * All this means that, for example, to say "read DLCR8" has no more
46 * than to say "read a register at offset 8 on bank DLCR."
47 *
48 * The following definitions may look silly, but that's what Fujitsu
49 * did, and it is necessary to know these names to read Fujitsu
50 * documents..
51 */
52
53 /* Data Link Control Registers, on invaliant port addresses. */
54 #define FE_DLCR0 0
55 #define FE_DLCR1 1
56 #define FE_DLCR2 2
57 #define FE_DLCR3 3
58 #define FE_DLCR4 4
59 #define FE_DLCR5 5
60 #define FE_DLCR6 6
61 #define FE_DLCR7 7
62
63 /* More DLCRs, on register bank #0. */
64 #define FE_DLCR8 8
65 #define FE_DLCR9 9
66 #define FE_DLCR10 10
67 #define FE_DLCR11 11
68 #define FE_DLCR12 12
69 #define FE_DLCR13 13
70 #define FE_DLCR14 14
71 #define FE_DLCR15 15
72
73 /* Multicast Address Registers. On register bank #1. */
74 #define FE_MAR8 8
75 #define FE_MAR9 9
76 #define FE_MAR10 10
77 #define FE_MAR11 11
78 #define FE_MAR12 12
79 #define FE_MAR13 13
80 #define FE_MAR14 14
81 #define FE_MAR15 15
82
83 /* Buffer Memory Port Registers. On register bank #2. */
84 #define FE_BMPR8 8
85 #define FE_BMPR9 9
86 #define FE_BMPR10 10
87 #define FE_BMPR11 11
88 #define FE_BMPR12 12
89 #define FE_BMPR13 13
90 #define FE_BMPR14 14
91 #define FE_BMPR15 15
92
93 /* More BMPRs, only on MB86965A, accessible only when JLI mode. */
94 #define FE_BMPR16 16
95 #define FE_BMPR17 17
96 #define FE_BMPR18 18
97 #define FE_BMPR19 19
98
99 #define FE_RESET 31
100
101 /*
102 * Definitions of registers.
103 * I don't have Fujitsu documents of MB86960A/MB86965A, so I don't
104 * know the official names for the flags and fields. The following
105 * names are assigned by me (the author of this file), since I cannot
106 * memorize hexadecimal constants for all of these functions.
107 * Comments? FIXME.
108 */
109
110 /* DLCR0 -- transmitter status */
111 #define FE_D0_BUSERR 0x01 /* Bus write error */
112 #define FE_D0_COLL16 0x02 /* Collision limit (16) encountered */
113 #define FE_D0_COLLID 0x04 /* Collision on last transmission */
114 #define FE_D0_JABBER 0x08 /* Jabber */
115 #define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */
116 #define FE_D0_PKTRCD 0x20 /* No collision on last transmission */
117 #define FE_D0_NETBSY 0x40 /* Network Busy (Carrier Detected) */
118 #define FE_D0_TXDONE 0x80 /* Transmission complete */
119
120 /* DLCR1 -- receiver status */
121 #define FE_D1_OVRFLO 0x01 /* Receiver buffer overflow */
122 #define FE_D1_CRCERR 0x02 /* CRC error on last packet */
123 #define FE_D1_ALGERR 0x04 /* Alignment error on last packet */
124 #define FE_D1_SRTPKT 0x08 /* Short (RUNT) packet is received */
125 #define FE_D1_RMTRST 0x10 /* Remote reset packet (type = 0x0900) */
126 #define FE_D1_DMAEOP 0x20 /* Host asserted End of DMA OPeration */
127 #define FE_D1_BUSERR 0x40 /* Bus read error */
128 #define FE_D1_PKTRDY 0x80 /* Packet(s) ready on receive buffer */
129
130 #define FE_D1_ERRBITS "\20\4SRTPKT\3ALGERR\2CRCERR\1OVRFLO"
131
132 /* DLCR2 -- transmitter interrupt control; same layout as DLCR0 */
133 #define FE_D2_BUSERR FE_D0_BUSERR
134 #define FE_D2_COLL16 FE_D0_COLL16
135 #define FE_D2_COLLID FE_D0_COLLID
136 #define FE_D2_JABBER FE_D0_JABBER
137 #define FE_D2_TXDONE FE_D0_TXDONE
138
139 #define FE_D2_RESERVED 0x70
140
141 /* DLCR3 -- receiver interrupt control; same layout as DLCR1 */
142 #define FE_D3_OVRFLO FE_D1_OVRFLO
143 #define FE_D3_CRCERR FE_D1_CRCERR
144 #define FE_D3_ALGERR FE_D1_ALGERR
145 #define FE_D3_SRTPKT FE_D1_SRTPKT
146 #define FE_D3_RMTRST FE_D1_RMTRST
147 #define FE_D3_DMAEOP FE_D1_DMAEOP
148 #define FE_D3_BUSERR FE_D1_BUSERR
149 #define FE_D3_PKTRDY FE_D1_PKTRDY
150
151 /* DLCR4 -- transmitter operation mode */
152 #define FE_D4_DSC 0x01 /* Disable carrier sense on trans. */
153 #define FE_D4_LBC 0x02 /* Loop back test control */
154 #define FE_D4_CNTRL 0x04 /* - ??? */
155 #define FE_D4_TEST1 0x08 /* Test output #1 */
156 #define FE_D4_COL 0xF0 /* Collision counter */
157
158 #define FE_D4_LBC_ENABLE 0x00 /* Perform loop back test */
159 #define FE_D4_LBC_DISABLE 0x02 /* Normal operation */
160
161 #define FE_D4_COL_SHIFT 4
162
163 /* DLCR5 -- receiver operation mode */
164 #define FE_D5_AFM0 0x01 /* Receive packets for other stations */
165 #define FE_D5_AFM1 0x02 /* Receive packets for this station */
166 #define FE_D5_RMTRST 0x04 /* Enable remote reset operation */
167 #define FE_D5_SRTPKT 0x08 /* Accept short (RUNT) packets */
168 #define FE_D5_SRTADR 0x10 /* Short (16 bits?) MAC address */
169 #define FE_D5_BADPKT 0x20 /* Accept packets with error */
170 #define FE_D5_BUFEMP 0x40 /* Receive buffer is empty */
171 #define FE_D5_TEST2 0x80 /* Test output #2 */
172
173 /* DLCR6 -- hardware configuration #0 */
174 #define FE_D6_BUFSIZ 0x03 /* Size of NIC buffer SRAM */
175 #define FE_D6_TXBSIZ 0x0C /* Size (and config)of trans. buffer */
176 #define FE_D6_BBW 0x10 /* Buffer SRAM bus width */
177 #define FE_D6_SBW 0x20 /* System bus width */
178 #define FE_D6_SRAM 0x40 /* Buffer SRAM access time */
179 #define FE_D6_DLC 0x80 /* Disable DLC (receiver/transmitter) */
180
181 #define FE_D6_BUFSIZ_8KB 0x00 /* The board has 8KB SRAM */
182 #define FE_D6_BUFSIZ_16KB 0x01 /* The board has 16KB SRAM */
183 #define FE_D6_BUFSIZ_32KB 0x02 /* The board has 32KB SRAM */
184 #define FE_D6_BUFSIZ_64KB 0x03 /* The board has 64KB SRAM */
185
186 #define FE_D6_TXBSIZ_1x2KB 0x00 /* Single 2KB buffer for trans. */
187 #define FE_D6_TXBSIZ_2x2KB 0x04 /* Double 2KB buffers */
188 #define FE_D6_TXBSIZ_2x4KB 0x08 /* Double 4KB buffers */
189 #define FE_D6_TXBSIZ_2x8KB 0x0C /* Double 8KB buffers */
190
191 #define FE_D6_BBW_WORD 0x00 /* SRAM has 16 bit data line */
192 #define FE_D6_BBW_BYTE 0x10 /* SRAM has 8 bit data line */
193
194 #define FE_D6_SBW_WORD 0x00 /* Access with 16 bit (AT) bus */
195 #define FE_D6_SBW_BYTE 0x20 /* Access with 8 bit (XT) bus */
196
197 #define FE_D6_SRAM_150ns 0x00 /* The board has slow SRAM */
198 #define FE_D6_SRAM_100ns 0x40 /* The board has fast SRAM */
199
200 #define FE_D6_DLC_ENABLE 0x00 /* Normal operation */
201 #define FE_D6_DLC_DISABLE 0x80 /* Stop sending/receiving */
202
203 /* DLC7 -- hardware configuration #1 */
204 #define FE_D7_BYTSWP 0x01 /* Host byte order control */
205 #define FE_D7_EOPPOL 0x02 /* Polarity of DMA EOP signal */
206 #define FE_D7_RBS 0x0C /* Register bank select */
207 #define FE_D7_RDYPNS 0x10 /* Senses RDYPNSEL input signal */
208 #define FE_D7_POWER 0x20 /* Stand-by (power down) mode control */
209 #define FE_D7_ED 0xC0 /* Encoder/Decoder config (for MB86960) */
210 #define FE_D7_IDENT 0xC0 /* Chip identification */
211
212 #define FE_D7_BYTSWP_LH 0x00 /* DEC/Intel byte order */
213 #define FE_D7_BYTSWP_HL 0x01 /* IBM/Motorolla byte order */
214
215 #define FE_D7_RBS_DLCR 0x00 /* Select DLCR8-15 */
216 #define FE_D7_RBS_MAR 0x04 /* Select MAR8-15 */
217 #define FE_D7_RBS_BMPR 0x08 /* Select BMPR8-15 */
218
219 #define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */
220 #define FE_D7_POWER_UP 0x20 /* Normal operation */
221
222 #define FE_D7_ED_NORMAL 0x00 /* Normal NICE */
223 #define FE_D7_ED_MON 0x40 /* NICE + Monitor */
224 #define FE_D7_ED_BYPASS 0x80 /* Encoder/Decorder Bypass */
225 #define FE_D7_ED_TEST 0xC0 /* Encoder/Decorder Test */
226
227 #define FE_D7_IDENT_86960 0x00 /* MB86960 (NICE) */
228 #define FE_D7_IDENT_86964 0x40 /* MB86964 */
229 #define FE_D7_IDENT_86967 0x80 /* MB86967 */
230 #define FE_D7_IDENT_86965 0xC0 /* MB86965 (EtherCoupler) */
231
232 /* DLCR8 thru DLCR13 are for Ethernet station address. */
233
234 /* DLCR14 and DLCR15 are for TDR (Time Domain Reflectometry). */
235
236 /* MAR8 thru MAR15 are for Multicast address filter. */
237
238 /* BMPR8 and BMPR9 are for packet data. */
239
240 /* BMPR10 -- transmitter start trigger */
241 #define FE_B10_START 0x80 /* Start transmitter */
242 #define FE_B10_COUNT 0x7F /* Packet count */
243
244 /* BMPR11 -- 16 collisions control */
245 #define FE_B11_CTRL 0x01 /* Skip or resend errored packets */
246 #define FE_B11_MODE1 0x02 /* Restart transmitter after COLL16 */
247 #define FE_B11_MODE2 0x04 /* Automatic restart enable */
248
249 #define FE_B11_CTRL_RESEND 0x00 /* Re-send the collided packet */
250 #define FE_B11_CTRL_SKIP 0x01 /* Skip the collided packet */
251
252 /* BMPR12 -- DMA enable */
253 #define FE_B12_TXDMA 0x01 /* Enable transmitter DMA */
254 #define FE_B12_RXDMA 0x02 /* Enable receiver DMA */
255
256 /* BMPR13 -- DMA control */
257 #define FE_B13_BSTCTL 0x03 /* DMA burst mode control */
258 #define FE_B13_TPTYPE 0x04 /* Twisted pair cable impedance */
259 #define FE_B13_PORT 0x18 /* Port (TP/AUI) selection */
260 #define FE_B13_LNKTST 0x20 /* Link test enable */
261 #define FE_B13_SQTHLD 0x40 /* Lower squelch threshold */
262 #define FE_B13_IOUNLK 0x80 /* Change I/O base address */
263
264 #define FE_B13_BSTCTL_1 0x00
265 #define FE_B13_BSTCTL_4 0x01
266 #define FE_B13_BSTCTL_8 0x02
267 #define FE_B13_BSTCLT_12 0x03
268
269 #define FE_B13_TPTYPE_UTP 0x00 /* Unshielded (standard) cable */
270 #define FE_B13_TPTYPE_STP 0x04 /* Shielded (IBM) cable */
271
272 #define FE_B13_PORT_AUTO 0x00 /* Auto detected */
273 #define FE_B13_PORT_TP 0x08 /* Force TP */
274 #define FE_B13_PORT_AUI 0x18 /* Force AUI */
275
276 /* BMPR14 -- More receiver control and more transmission interrupts */
277 #define FE_B14_FILTER 0x01 /* Filter out self-originated packets */
278 #define FE_B14_SQE 0x02 /* SQE interrupt enable */
279 #define FE_B14_SKIP 0x04 /* Skip a received packet */
280 #define FE_B14_RJAB 0x20 /* RJAB interrupt enable */
281 #define FE_B14_LLD 0x40 /* Local-link-down interrupt enable */
282 #define FE_B14_RLD 0x80 /* Remote-link-down interrupt enable */
283
284 /* BMPR15 -- More transmitter status; basically same layout as BMPR14 */
285 #define FE_B15_SQE FE_B14_SQE
286 #define FE_B15_RCVPOL 0x08 /* Reversed receive line polarity */
287 #define FE_B15_RMTPRT 0x10 /* ??? */
288 #define FE_B15_RAJB FE_B14_RJAB
289 #define FE_B15_LLD FE_B14_LLD
290 #define FE_B15_RLD FE_B14_RLD
291
292 /* BMPR16 -- EEPROM control */
293 #define FE_B16_DOUT 0x04 /* EEPROM Data in (CPU to EEPROM) */
294 #define FE_B16_SELECT 0x20 /* EEPROM chip select */
295 #define FE_B16_CLOCK 0x40 /* EEPROM shift clock */
296 #define FE_B16_DIN 0x80 /* EEPROM data out (EEPROM to CPU) */
297
298 /* BMPR17 -- EEPROM data */
299 #define FE_B17_DATA 0x80 /* EEPROM data bit */
300
301 /* BMPR18 I/O Base Address (Only JLI mode) */
302
303 /* BMPR19 -- Jumperless Setting (Only JLI mode) */
304 #define FE_B19_IRQ 0xC0
305 #define FE_B19_IRQ_SHIFT 6
306
307 #define FE_B19_ROM 0x38
308 #define FE_B19_ROM_SHIFT 3
309
310 #define FE_B19_ADDR 0x07
311 #define FE_B19_ADDR_SHIFT 0
312
313 /*
314 * EEPROM specification (of JLI mode).
315 */
316
317 /* Number of bytes in an EEPROM accessible through 86965. */
318 #define FE_EEPROM_SIZE 32
319
320 /* Offset for JLI config; automatically copied into BMPR19 at startup. */
321 #define FE_EEPROM_CONF 0x00
322
323 /* Delay for 93c06 EEPROM access */
324 #define FE_EEPROM_DELAY() DELAY(4)
325
326 /*
327 * EEPROM allocation of AT1700/RE2000.
328 */
329 #define FE_ATI_EEP_ADDR 0x08 /* Station address (0x08-0x0d) */
330 #define FE_ATI_EEP_MEDIA 0x18 /* Media type */
331 #define FE_ATI_EEP_MAGIC 0x19 /* XXX Magic */
332 #define FE_ATI_EEP_MODEL 0x1e /* Hardware type */
333 #define FE_ATI_MODEL_AT1700T 0x00
334 #define FE_ATI_MODEL_AT1700BT 0x01
335 #define FE_ATI_MODEL_AT1700FT 0x02
336 #define FE_ATI_MODEL_AT1700AT 0x03
337 #define FE_ATI_EEP_REVISION 0x1f /* Hardware revision */
338
339 /*
340 * Some 86960 specific constants.
341 */
342
343 /* Length (in bytes) of a Multicast Address Filter. */
344 #define FE_FILTER_LEN 8
345
346 /* How many packets we can put in the transmission buffer on NIC memory. */
347 #define FE_QUEUEING_MAX 127
348
349 /* Size (in bytes) of a "packet length" word in transmission buffer. */
350 #define FE_TXLEN_SIZE 2
351
352 /* receive packet status in the receive packet header. */
353 #define FE_RXSTAT_GOODPKT 0x20
354 #define FE_RXSTAT_RMT0900 0x10
355 #define FE_RXSTAT_SHORTPKT 0x08
356 #define FE_RXSTAT_ALIGNERR 0x04
357 #define FE_RXSTAT_CRCERR 0x02
358
359 /*
360 * FUJITSU MBH10302 specific Registers.
361 */
362
363 #define FE_MBH0 0x10 /* Master interrupt register */
364 #define FE_MBH_ENADDR 0x1A /* Mac address */
365 #define FE_MBH0_MASK 0x0D
366 #define FE_MBH0_INTR_ENABLE 0x10 /* Enable interrupts */
367
368 #endif /* MB86960REG_H */
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