/[gxemul]/trunk/src/include/m8820x.h
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Contents of /trunk/src/include/m8820x.h

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Revision 42 - (show annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 8006 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============
1 /* GXemul: $Id: m8820x.h,v 1.1 2007/05/15 12:35:14 debug Exp $ */
2 /* $OpenBSD: m8820x.h,v 1.7 2006/05/06 16:59:26 miod Exp $ */
3 /*
4 * Copyright (c) 2004, Miodrag Vallat.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27 /*
28 * Mach Operating System
29 * Copyright (c) 1993-1992 Carnegie Mellon University
30 * All Rights Reserved.
31 *
32 * Permission to use, copy, modify and distribute this software and its
33 * documentation is hereby granted, provided that both the copyright
34 * notice and this permission notice appear in all copies of the
35 * software, derivative works or modified versions, and any portions
36 * thereof, and that both notices appear in supporting documentation.
37 *
38 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
39 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
40 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
41 *
42 * Carnegie Mellon requests users of this software to return to
43 *
44 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
45 * School of Computer Science
46 * Carnegie Mellon University
47 * Pittsburgh PA 15213-3890
48 *
49 * any improvements or extensions that they make and grant Carnegie Mellon
50 * the rights to redistribute these changes.
51 */
52
53 #ifndef __M88K_M8820X_H__
54 #define __M88K_M8820X_H__
55
56 /*
57 * 8820x CMMU definitions
58 */
59
60 /* CMMU registers */
61 #define CMMU_IDR (0x000 / 4) /* CMMU id register */
62 #define CMMU_SCR (0x004 / 4) /* system command register */
63 #define CMMU_SSR (0x008 / 4) /* system status register */
64 #define CMMU_SAR (0x00c / 4) /* system address register */
65 #define CMMU_SCTR (0x104 / 4) /* system control register */
66 #define CMMU_PFSR (0x108 / 4) /* P bus fault status register */
67 #define CMMU_PFAR (0x10c / 4) /* P bus fault address register */
68 #define CMMU_SAPR (0x200 / 4) /* supervisor area pointer register */
69 #define CMMU_UAPR (0x204 / 4) /* user area pointer register */
70 #define CMMU_BWP0 (0x400 / 4) /* block ATC writer port 0 */
71 #define CMMU_BWP1 (0x404 / 4) /* block ATC writer port 1 */
72 #define CMMU_BWP2 (0x408 / 4) /* block ATC writer port 2 */
73 #define CMMU_BWP3 (0x40c / 4) /* block ATC writer port 3 */
74 #define CMMU_BWP4 (0x410 / 4) /* block ATC writer port 4 */
75 #define CMMU_BWP5 (0x414 / 4) /* block ATC writer port 5 */
76 #define CMMU_BWP6 (0x418 / 4) /* block ATC writer port 6 */
77 #define CMMU_BWP7 (0x41c / 4) /* block ATC writer port 7 */
78 #define CMMU_BWP(n) (CMMU_BWP0 + (n))
79 #define CMMU_CDP0 (0x800 / 4) /* cache data port 0 */
80 #define CMMU_CDP1 (0x804 / 4) /* cache data port 1 */
81 #define CMMU_CDP2 (0x808 / 4) /* cache data port 2 */
82 #define CMMU_CDP3 (0x80c / 4) /* cache data port 3 */
83 #define CMMU_CTP0 (0x840 / 4) /* cache tag port 0 */
84 #define CMMU_CTP1 (0x844 / 4) /* cache tag port 1 */
85 #define CMMU_CTP2 (0x848 / 4) /* cache tag port 2 */
86 #define CMMU_CTP3 (0x84c / 4) /* cache tag port 3 */
87 #define CMMU_CSSP0 (0x880 / 4) /* cache set status register */
88 #define CMMU_CSSP(n) ((0x880 + (n * 0x10)) / 4)
89 /* the following only exist on 88204 */
90 #define CMMU_CSSP1 (0x890 / 4) /* cache set status register */
91 #define CMMU_CSSP2 (0x8a0 / 4) /* cache set status register */
92 #define CMMU_CSSP3 (0x8b0 / 4) /* cache set status register */
93
94 /* system commands */
95 #define CMMU_FLUSH_CACHE_INV_LINE 0x14 /* data cache invalidate */
96 #define CMMU_FLUSH_CACHE_INV_PAGE 0x15
97 #define CMMU_FLUSH_CACHE_INV_SEGMENT 0x16
98 #define CMMU_FLUSH_CACHE_INV_ALL 0x17
99 #define CMMU_FLUSH_CACHE_CB_LINE 0x18 /* data cache copyback */
100 #define CMMU_FLUSH_CACHE_CB_PAGE 0x19
101 #define CMMU_FLUSH_CACHE_CB_SEGMENT 0x1a
102 #define CMMU_FLUSH_CACHE_CB_ALL 0x1b
103 #define CMMU_FLUSH_CACHE_CBI_LINE 0x1c /* copyback and invalidate */
104 #define CMMU_FLUSH_CACHE_CBI_PAGE 0x1d
105 #define CMMU_FLUSH_CACHE_CBI_SEGMENT 0x1e
106 #define CMMU_FLUSH_CACHE_CBI_ALL 0x1f
107 #define CMMU_PROBE_USER 0x20 /* probe user address */
108 #define CMMU_PROBE_SUPER 0x24 /* probe supervisor address */
109 #define CMMU_FLUSH_USER_LINE 0x30 /* flush PATC */
110 #define CMMU_FLUSH_USER_PAGE 0x31
111 #define CMMU_FLUSH_USER_SEGMENT 0x32
112 #define CMMU_FLUSH_USER_ALL 0x33
113 #define CMMU_FLUSH_SUPER_LINE 0x34
114 #define CMMU_FLUSH_SUPER_PAGE 0x35
115 #define CMMU_FLUSH_SUPER_SEGMENT 0x36
116 #define CMMU_FLUSH_SUPER_ALL 0x37
117
118 /* system control values */
119 #define CMMU_SCTR_PE 0x00008000 /* parity enable */
120 #define CMMU_SCTR_SE 0x00004000 /* snoop enable */
121 #define CMMU_SCTR_PR 0x00002000 /* priority arbitration */
122
123 /* P bus fault status */
124 #define CMMU_PFSR_FAULT(pfsr) (((pfsr) >> 16) & 0x07)
125 #define CMMU_PFSR_SUCCESS 0 /* no fault */
126 #define CMMU_PFSR_BERROR 3 /* bus error */
127 #define CMMU_PFSR_SFAULT 4 /* segment fault */
128 #define CMMU_PFSR_PFAULT 5 /* page fault */
129 #define CMMU_PFSR_SUPER 6 /* supervisor violation */
130 #define CMMU_PFSR_WRITE 7 /* writer violation */
131
132 /* CSSP values */
133 #define CMMU_CSSP_L5 0x20000000
134 #define CMMU_CSSP_L4 0x10000000
135 #define CMMU_CSSP_L3 0x08000000
136 #define CMMU_CSSP_L2 0x04000000
137 #define CMMU_CSSP_L1 0x02000000
138 #define CMMU_CSSP_L0 0x01000000
139 #define CMMU_CSSP_D3 0x00800000
140 #define CMMU_CSSP_D2 0x00400000
141 #define CMMU_CSSP_D1 0x00200000
142 #define CMMU_CSSP_D0 0x00100000
143 #define CMMU_CSSP_VV(n,v) (((v) & 0x03) << (12 + 2 * (n)))
144 #define CMMU_VV_EXCLUSIVE 0x00
145 #define CMMU_VV_MODIFIED 0x01
146 #define CMMU_VV_SHARED 0x02
147 #define CMMU_VV_INVALID 0x03
148
149 /* IDR values */
150 #define CMMU_ID(idr) ((idr) >> 24)
151 #define CMMU_TYPE(idr) (((idr) >> 21) & 0x07)
152 #define CMMU_VERSION(idr) (((idr) >> 16) & 0x1f)
153 #define M88200_ID 5
154 #define M88204_ID 6
155
156 /* SSR values */
157 #define CMMU_SSR_CE 0x00008000 /* copyback error */
158 #define CMMU_SSR_BE 0x00004000 /* bus error */
159 #define CMMU_SSR_SO 0x00000100
160 #define CMMU_SSR_M 0x00000010
161 #define CMMU_SSR_U 0x00000008
162 #define CMMU_SSR_PROT 0x00000004
163 #define CMMU_SSR_BH 0x00000002 /* probe BATC hit */
164 #define CMMU_SSR_V 0x00000001
165
166 /*
167 * Cache line information
168 */
169
170 #define MC88200_CACHE_SHIFT 4
171 #define MC88200_CACHE_LINE (1 << MC88200_CACHE_SHIFT)
172
173 /*
174 * Hardwired BATC information
175 */
176
177 #define BATC8 0xfff7ffb5
178 #define BATC9 0xfffffff5
179
180 #define BATC8_VA 0xfff00000
181 #define BATC9_VA 0xfff80000
182
183 #define NBSG (1 << (PDT_BITS + PG_BITS)) /* segment size */
184
185 #define INST_CMMU 0x00 /* even number */
186 #define DATA_CMMU 0x01 /* odd number */
187 #define CMMU_MODE(num) ((num) & 1)
188
189 #define MAX_CMMUS 8 /* maximum cmmus on the board */
190
191 #if 0
192 #ifndef _LOCORE
193
194 /*
195 * CMMU kernel information
196 */
197 struct m8820x_cmmu {
198 volatile u_int32_t *cmmu_regs; /* CMMU "base" area */
199 #ifdef M88200_HAS_SPLIT_ADDRESS
200 vaddr_t cmmu_addr; /* address range */
201 vaddr_t cmmu_addr_mask; /* address mask */
202 #endif
203 };
204
205 extern struct m8820x_cmmu m8820x_cmmu[MAX_CMMUS];
206 extern u_int cmmu_shift;
207 extern u_int max_cmmus;
208
209 void m8820x_setup_board_config(void);
210 cpuid_t m8820x_cpu_number(void);
211
212 #endif /* _LOCORE */
213 #endif
214
215 #endif /* __M88K_M8820X_H__ */
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