/[gxemul]/trunk/src/include/if_mecreg.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/include/if_mecreg.h

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Revision 4 - (show annotations)
Mon Oct 8 16:18:00 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 6191 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============
1 /* gxemul: $Id: if_mecreg.h,v 1.2 2005/03/05 12:34:02 debug Exp $ */
2 /* $NetBSD: if_mecreg.h,v 1.2 2004/07/11 03:13:04 tsutsui Exp $ */
3
4 #ifndef IF_MECREG_H
5 #define IF_MECREG_H
6
7 /*
8 * Copyright (c) 2001 Christopher Sekiya
9 * Copyright (c) 2000 Soren S. Jorvang
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed for the
23 * NetBSD Project. See http://www.NetBSD.org/ for
24 * information about NetBSD.
25 * 4. The name of the author may not be used to endorse or promote products
26 * derived from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
31 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * MACE MAC110 ethernet register definitions
42 */
43
44 #define MEC_MAC_CONTROL 0x00
45 #define MEC_MAC_CORE_RESET 0x0000000000000001 /* reset signal */
46 #define MEC_MAC_FULL_DUPLEX 0x0000000000000002 /* 1 to enable */
47 #define MEC_MAC_INT_LOOPBACK 0x0000000000000004 /* 0 = normal op */
48 #define MEC_MAC_SPEED_SELECT 0x0000000000000008 /* 0/1 10/100 */
49 #define MEC_MAC_MII_SELECT 0x0000000000000010 /* MII/SIA */
50 #define MEC_MAC_FILTER_MASK 0x0000000000000060
51 #define MEC_MAC_FILTER_STATION 0x0000000000000000
52 #define MEC_MAC_FILTER_MATCHMULTI 0x0000000000000020
53 #define MEC_MAC_FILTER_ALLMULTI 0x0000000000000040
54 #define MEC_MAC_FILTER_PROMISC 0x0000000000000060
55 #define MEC_MAC_LINK_FAILURE 0x0000000000000080
56 #define MEC_MAC_IPGT 0x0000000000007f00 /* interpacket gap */
57 #define MEC_MAC_IPGT_SHIFT 8
58 #define MEC_MAC_IPGR1 0x00000000003f8000
59 #define MEC_MAC_IPGR1_SHIFT 15
60 #define MEC_MAC_IPGR2 0x000000001fc00000
61 #define MEC_MAC_IPGR2_SHIFT 22
62 #define MEC_MAC_REVISION 0x00000000e0000000
63 #define MEC_MAC_REVISION_SHIFT 29
64
65 #define MEC_MAC_IPG_DEFAULT \
66 (21 << MEC_MAC_IPGT_SHIFT) | \
67 (17 << MEC_MAC_IPGR1_SHIFT) | \
68 (11 << MEC_MAC_IPGR2_SHIFT)
69
70 #define MEC_INT_STATUS 0x08
71 #define MEC_INT_STATUS_MASK 0x00000000000000ff
72 #define MEC_INT_TX_EMPTY 0x0000000000000001
73 #define MEC_INT_TX_PACKET_SENT 0x0000000000000002
74 #define MEC_INT_TX_LINK_FAIL 0x0000000000000004
75 #define MEC_INT_TX_MEM_ERROR 0x0000000000000008
76 #define MEC_INT_TX_ABORT 0x0000000000000010
77 #define MEC_INT_RX_THRESHOLD 0x0000000000000020
78 #define MEC_INT_RX_FIFO_UNDERFLOW 0x0000000000000040
79 #define MEC_INT_RX_DMA_UNDERFLOW 0x0000000000000080
80 #define MEC_INT_RX_MCL_FIFO_ALIAS 0x0000000000001f00
81 #define MEC_INT_TX_RING_BUFFER_ALIAS 0x0000000001ff0000
82 #define MEC_INT_RX_SEQUENCE_NUMBER 0x000000003e000000
83 #define MEC_INT_MCAST_HASH_OUTPUT 0x0000000040000000
84
85 #define MEC_DMA_CONTROL 0x10
86 #define MEC_DMA_TX_INT_ENABLE 0x0000000000000001
87 #define MEC_DMA_TX_DMA_ENABLE 0x0000000000000002
88 #define MEC_DMA_TX_RING_SIZE_MASK 0x000000000000000c
89 #define MEC_DMA_RX_INT_THRESHOLD 0x00000000000001f0
90 #define MEC_DMA_RX_INT_THRESH_SHIFT 4
91 #define MEC_DMA_RX_INT_ENABLE 0x0000000000000200
92 #define MEC_DMA_RX_RUNT 0x0000000000000400
93 #define MEC_DMA_RX_PACKET_GATHER 0x0000000000000800
94 #define MEC_DMA_RX_DMA_OFFSET 0x0000000000007000
95 #define MEC_DMA_RX_DMA_OFFSET_SHIFT 12
96 #define MEC_DMA_RX_DMA_ENABLE 0x0000000000008000
97
98 #define MEC_TIMER 0x18
99 #define MEC_TX_ALIAS 0x20
100 #define MEC_TX_ALIAS_INT_ENABLE 0x0000000000000001
101
102 #define MEC_RX_ALIAS 0x28
103 #define MEC_RX_ALIAS_INT_ENABLE 0x0000000000000200
104 #define MEC_RX_ALIAS_INT_THRESHOLD 0x00000000000001f0
105
106 #define MEC_TX_RING_PTR 0x30
107 #define MEC_TX_RING_WRITE_PTR 0x00000000000001ff
108 #define MEC_TX_RING_READ_PTR 0x0000000001ff0000
109 #define MEC_TX_RING_PTR_ALIAS 0x38
110
111 #define MEC_RX_FIFO 0x40
112 #define MEC_RX_FIFO_ELEMENT_COUNT 0x000000000000001f
113 #define MEC_RX_FIFO_READ_PTR 0x0000000000000f00
114 #define MEC_RX_FIFO_GEN_NUMBER 0x0000000000001000
115 #define MEC_RX_FIFO_WRITE_PTR 0x00000000000f0000
116 #define MEC_RX_FIFO_GEN_NUMBER_2 0x0000000000100000
117
118 #define MEC_RX_FIFO_ALIAS1 0x48
119 #define MEC_RX_FIFO_ALIAS2 0x50
120 #define MEC_TX_VECTOR 0x58
121 #define MEC_IRQ_VECTOR 0x58
122
123 #define MEC_PHY_DATA_PAD 0x60 /* XXX ? */
124 #define MEC_PHY_DATA 0x64
125 #define MEC_PHY_DATA_BUSY 0x00010000
126 #define MEC_PHY_DATA_VALUE 0x0000ffff
127
128 #define MEC_PHY_ADDRESS_PAD 0x68 /* XXX ? */
129 #define MEC_PHY_ADDRESS 0x6c
130 #define MEC_PHY_ADDR_REGISTER 0x0000001f
131 #define MEC_PHY_ADDR_DEVICE 0x000003e0
132 #define MEC_PHY_ADDR_DEVSHIFT 5
133
134 #define MEC_PHY_READ_INITIATE 0x70
135 #define MEC_PHY_BACKOFF 0x78
136
137 #define MEC_STATION 0xa0
138 #define MEC_STATION_ALT 0xa8
139 #define MEC_STATION_MASK 0x0000ffffffffffffULL
140
141 #define MEC_MULTICAST 0xb0
142 #define MEC_TX_RING_BASE 0xb8
143 #define MEC_TX_PKT1_CMD_1 0xc0
144 #define MEC_TX_PKT1_BUFFER_1 0xc8
145 #define MEC_TX_PKT1_BUFFER_2 0xd0
146 #define MEC_TX_PKT1_BUFFER_3 0xd8
147 #define MEC_TX_PKT2_CMD_1 0xe0
148 #define MEC_TX_PKT2_BUFFER_1 0xe8
149 #define MEC_TX_PKT2_BUFFER_2 0xf0
150 #define MEC_TX_PKT2_BUFFER_3 0xf8
151
152 #define MEC_MCL_RX_FIFO 0x100
153
154 #endif /* IF_MECREG_H */
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