/[gxemul]/trunk/src/include/i8253reg.h
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Annotation of /trunk/src/include/i8253reg.h

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Revision 28 - (hide annotations)
Mon Oct 8 16:20:26 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 4734 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============
1 dpavlin 28 /* GXemul: $Id: i8253reg.h,v 1.1 2006/07/18 19:48:03 debug Exp $ */
2     /* $NetBSD: i8253reg.h,v 1.9 2005/12/11 12:21:26 christos Exp $ */
3    
4     #ifndef I8253REG_H
5     #define I8253REG_H
6    
7     /*-
8     * Copyright (c) 1993 The Regents of the University of California.
9     * All rights reserved.
10     *
11     * Redistribution and use in source and binary forms, with or without
12     * modification, are permitted provided that the following conditions
13     * are met:
14     * 1. Redistributions of source code must retain the above copyright
15     * notice, this list of conditions and the following disclaimer.
16     * 2. Redistributions in binary form must reproduce the above copyright
17     * notice, this list of conditions and the following disclaimer in the
18     * documentation and/or other materials provided with the distribution.
19     * 3. Neither the name of the University nor the names of its contributors
20     * may be used to endorse or promote products derived from this software
21     * without specific prior written permission.
22     *
23     * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26     * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33     * SUCH DAMAGE.
34     */
35    
36     /*
37     * Register definitions for the Intel 8253 Programmable Interval Timer.
38     *
39     * This chip has three independent 16-bit down counters that can be
40     * read on the fly. There are three mode registers and three countdown
41     * registers. The countdown registers are addressed directly, via the
42     * first three I/O ports. The three mode registers are accessed via
43     * the fourth I/O port, with two bits in the mode byte indicating the
44     * register. (Why are hardware interfaces always so braindead?).
45     *
46     * To write a value into the countdown register, the mode register
47     * is first programmed with a command indicating the which byte of
48     * the two byte register is to be modified. The three possibilities
49     * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then
50     * msb (TMR_MR_BOTH).
51     *
52     * To read the current value ("on the fly") from the countdown register,
53     * you write a "latch" command into the mode register, then read the stable
54     * value from the corresponding I/O port. For example, you write
55     * TMR_MR_LATCH into the corresponding mode register. Presumably,
56     * after doing this, a write operation to the I/O port would result
57     * in undefined behavior (but hopefully not fry the chip).
58     * Reading in this manner has no side effects.
59     *
60     * The outputs of the three timers are connected as follows:
61     *
62     * timer 0 -> irq 0
63     * timer 1 -> DMA chan 0 (for dram refresh)
64     * timer 2 -> speaker (via keyboard controller)
65     *
66     * Timer 0 is used to call hardclock.
67     * Timer 2 is used to generate console beeps.
68     */
69    
70     /*
71     * Frequency of all three count-down timers; (I8253_TIMER_FREQ/freq) is the
72     * appropriate count to generate a frequency of freq Hz.
73     */
74     #ifndef I8253_TIMER_FREQ
75     #define I8253_TIMER_FREQ 1193182
76     #endif
77     #define I8253_TIMER_DIV(x) ((I8253_TIMER_FREQ+(x)/2)/(x))
78    
79     /*
80     * Macros for specifying values to be written into a mode register.
81     */
82     #define I8253_TIMER_CNTR0 0 /* timer 0 counter port */
83     #define I8253_TIMER_CNTR1 1 /* timer 1 counter port */
84     #define I8253_TIMER_CNTR2 2 /* timer 2 counter port */
85     #define I8253_TIMER_MODE 3 /* timer mode port */
86     #define I8253_TIMER_SEL0 0x00 /* select counter 0 */
87     #define I8253_TIMER_SEL1 0x40 /* select counter 1 */
88     #define I8253_TIMER_SEL2 0x80 /* select counter 2 */
89     #define I8253_TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */
90     #define I8253_TIMER_ONESHOT 0x02 /* mode 1, one shot */
91     #define I8253_TIMER_RATEGEN 0x04 /* mode 2, rate generator */
92     #define I8253_TIMER_SQWAVE 0x06 /* mode 3, square wave */
93     #define I8253_TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */
94     #define I8253_TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */
95     #define I8253_TIMER_LATCH 0x00 /* latch counter for reading */
96     #define I8253_TIMER_LSB 0x10 /* r/w counter LSB */
97     #define I8253_TIMER_MSB 0x20 /* r/w counter MSB */
98     #define I8253_TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */
99     #define I8253_TIMER_BCD 0x01 /* count in BCD */
100    
101     #endif /* I8253REG_H */
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