/[gxemul]/trunk/src/include/gtreg.h
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Contents of /trunk/src/include/gtreg.h

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Revision 30 - (show annotations)
Mon Oct 8 16:20:40 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 3178 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1325 2006/08/15 15:38:37 debug Exp $
20060723	More Transputer instructions (pfix, nfix, opr, mint, ldl, ldlp,
		eqc, rev, ajw, stl, stlf, sthf, sub, ldnl, ldnlp, ldpi, move,
		wcnt, add, bcnt).
		Adding more SPARC instructions (andcc, addcc, bl, rdpr).
		Progress on the igsfb framebuffer used by NetBSD/netwinder.
		Enabling 8-bit fills in dev_fb.
		NetBSD/netwinder 3.0.1 can now run from a disk image :-)
20060724	Cleanup/performance fix for 64-bit virtual translation table
		updates (by removing the "timestamp" stuff). A full NetBSD/pmax
		3.0.1 install for R4400 has dropped from 667 seconds to 584 :)
		Fixing the igsfb "almost vga" color (it is 24-bit, not 18-bit).
		Adding some MIPS instruction combinations (3*lw, and 3*addu).
		The 8048 keyboard now turns off interrupt enable between the
		KBR_ACK and the KBR_RSTDONE, to work better with Linux 2.6.
		Not causing PPC DEC interrupts if PPC_NO_DEC is set for a
		specific CPU; NetBSD/bebox gets slightly further than before.
		Adding some more SPARC instructions: branches, udiv.
20060725	Refreshing dev_pckbc.c a little.
		Cleanups for the SH emulation mode, and adding the first
		"compact" (16-bit) instructions: various simple movs, nop,
		shll, stc, or, ldc.
20060726	Adding dummy "pcn" (AMD PCnet NIC) PCI glue.
20060727	Various cleanups; removing stuff from cpu.h, such as
		running_translated (not really meaningful anymore), and
		page flags (breaking into the debugger clears all translations
		anyway).
		Minor MIPS instruction combination updates.
20060807	Expanding the 3*sw and 3*lw MIPS instruction combinations to
		work with 2* and 4* too, resulting in a minor performance gain.
		Implementing a usleep hack for the RM52xx/MIPS32/MIPS64 "wait"
		instruction (when emulating 1 cpu).
20060808	Experimenting with some more MIPS instruction combinations.
		Implementing support for showing a (hardcoded 12x22) text
		cursor in igsfb.
20060809	Simplifying the NetBSD/evbmips (Malta) install instructions
		somewhat (by using a NetBSD/pmax ramdisk install kernel).
20060812	Experimenting more with the MIPS 'wait' instruction.
		PCI configuration register writes can now be handled, which
		allow PCI IDE controllers to work with NetBSD/Malta 3.0.1 and
		NetBSD/cobalt 3.0.1. (Previously only NetBSD 2.1 worked.)
20060813	Updating dev_gt.c based on numbers from Alec Voropay, to enable
		Linux 2.6 to use PCI on Malta.
		Continuing on Algor interrupt stuff.
20060814	Adding support for routing ISA interrupts to two different
		interrupts, making it possible to run NetBSD/algor :-)
20060814-15	Testing for the release.

==============  RELEASE 0.4.2  ==============


1 /* GXemul: $Id: gtreg.h,v 1.2 2006/08/13 08:34:06 debug Exp $ */
2 /* $NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $ */
3
4 /*
5 * This is basically malta/dev/gtreg.h from NetBSD, with additional
6 * defines that Linux uses. Symbol names are practically the same in
7 * NetBSD and Linux, which simplifies things.
8 */
9
10 #ifndef GTREG_H
11 #define GTREG_H
12
13 #define GT_REGVAL(x) *((volatile u_int32_t *) \
14 (MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x))))
15
16 /* CPU Configuration Register Map */
17 #define GT_CPU_INT 0x000
18 #define GT_MULTIGT 0x120
19
20 /* CPU Address Decode Register Map */
21 #define GT_PCI0IOLD_OFS 0x048
22 #define GT_PCI0IOHD_OFS 0x050
23 #define GT_PCI0M0LD_OFS 0x058
24 #define GT_PCI0M0HD_OFS 0x060
25 #define GT_PCI0M1LD_OFS 0x080
26 #define GT_PCI0M1HD_OFS 0x088
27 #define GT_PCI0IOREMAP_OFS 0x0f0
28 #define GT_PCI0M0REMAP_OFS 0x0f8
29 #define GT_PCI0M1REMAP_OFS 0x100
30
31 #define GT_N_DECODE_REGS (0x108 / 8)
32
33 /* CPU Error Report Register Map */
34
35 /* CPU Sync Barrier Register Map */
36
37 /* SDRAM and Device Address Decode Register Map */
38
39 /* SDRAM Configuration Register Map */
40
41 /* SDRAM Parameters Register Map */
42
43 /* ECC Register Map */
44
45 /* Device Parameters Register Map */
46
47 /* DMA Record Register Map */
48
49 /* DMA Arbiter Register Map */
50
51 /* Timer/Counter Register Map */
52 //#define GT_TC_0 0x850
53 //#define GT_TC_1 0x854
54 //#define GT_TC_2 0x858
55 //#define GT_TC_3 0x85c
56 //#define GT_TC_CONTROL 0x864
57
58 /* PCI Internal Register Map */
59 #define GT_PCI0_CMD_OFS 0xc00
60 #define GT_PCI0_CFG_ADDR 0xcf8
61 #define GT_PCI0_CFG_DATA 0xcfc
62 #define GT_PCI0_INTR_ACK 0xc34
63
64 /* Interrupts Register Map */
65 #define GT_INTR_CAUSE 0xc18
66 #define GTIC_INTSUM 0x00000001
67 #define GTIC_MEMOUT 0x00000002
68 #define GTIC_DMAOUT 0x00000004
69 #define GTIC_CPUOUT 0x00000008
70 #define GTIC_DMA0COMP 0x00000010
71 #define GTIC_DMA1COMP 0x00000020
72 #define GTIC_DMA2COMP 0x00000040
73 #define GTIC_DMA3COMP 0x00000080
74 #define GTIC_T0EXP 0x00000100
75 #define GTIC_T1EXP 0x00000200
76 #define GTIC_T2EXP 0x00000400
77 #define GTIC_T3EXP 0x00000800
78 #define GTIC_MASRDERR0 0x00001000
79 #define GTIC_SLVWRERR0 0x00002000
80 #define GTIC_MASWRERR0 0x00004000
81 #define GTIC_SLVRDERR0 0x00008000
82 #define GTIC_ADDRERR0 0x00010000
83 #define GTIC_MEMERR 0x00020000
84 #define GTIC_MASABORT0 0x00040000
85 #define GTIC_TARABORT0 0x00080000
86 #define GTIC_RETRYCNT0 0x00100000
87 #define GTIC_PMCINT_0 0x00200000
88 #define GTIC_CPUINT 0x0c300000
89 #define GTIC_PCINT 0xc3000000
90 #define GTIC_CPUINTSUM 0x40000000
91 #define GTIC_PCIINTSUM 0x80000000
92
93 /* PCI Configuration Register Map */
94 //#define GT_PCICONFIGBASE 0
95 //#define GT_PCIDID BONITO(GT_PCICONFIGBASE + 0x00)
96 //#define GT_PCICMD BONITO(GT_PCICONFIGBASE + 0x04)
97 //#define GT_PCICLASS BONITO(GT_PCICONFIGBASE + 0x08)
98 //#define GT_PCILTIMER BONITO(GT_PCICONFIGBASE + 0x0c)
99 //#define GT_PCIBASE0 BONITO(GT_PCICONFIGBASE + 0x10)
100 //#define GT_PCIBASE1 BONITO(GT_PCICONFIGBASE + 0x14)
101 //#define GT_PCIBASE2 BONITO(GT_PCICONFIGBASE + 0x18)
102 //#define GT_PCIEXPRBASE BONITO(GT_PCICONFIGBASE + 0x30)
103 //#define GT_PCIINT BONITO(GT_PCICONFIGBASE + 0x3c)
104
105 /* PCI Configuration, Function 1, Register Map */
106
107 /* I2O Support Register Map */
108
109 #endif /* !GTREG_H */

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