/[gxemul]/trunk/src/include/gtreg.h
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Contents of /trunk/src/include/gtreg.h

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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 3627 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 /* GXemul: $Id: gtreg.h,v 1.3 2006/09/23 03:52:10 debug Exp $ */
2 /* $NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $ */
3
4 /*
5 * This is basically malta/dev/gtreg.h from NetBSD, with additional
6 * defines that Linux uses. Symbol names are practically the same in
7 * NetBSD and Linux, which simplifies things.
8 *
9 * Also parts from cobalt/dev/gtreg.h from NetBSD.
10 *
11 * TODO: Find a better gtreg.h.
12 */
13
14 #ifndef GTREG_H
15 #define GTREG_H
16
17 #define GT_REGVAL(x) *((volatile u_int32_t *) \
18 (MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x))))
19
20 /* CPU Configuration Register Map */
21 #define GT_CPU_INT 0x000
22 #define GT_MULTIGT 0x120
23
24 /* CPU Address Decode Register Map */
25 #define GT_PCI0IOLD_OFS 0x048
26 #define GT_PCI0IOHD_OFS 0x050
27 #define GT_PCI0M0LD_OFS 0x058
28 #define GT_PCI0M0HD_OFS 0x060
29 #define GT_PCI0M1LD_OFS 0x080
30 #define GT_PCI0M1HD_OFS 0x088
31 #define GT_PCI0IOREMAP_OFS 0x0f0
32 #define GT_PCI0M0REMAP_OFS 0x0f8
33 #define GT_PCI0M1REMAP_OFS 0x100
34
35 #define GT_N_DECODE_REGS (0x108 / 8)
36
37 /* CPU Error Report Register Map */
38
39 /* CPU Sync Barrier Register Map */
40
41 /* SDRAM and Device Address Decode Register Map */
42
43 /* SDRAM Configuration Register Map */
44
45 /* SDRAM Parameters Register Map */
46
47 /* ECC Register Map */
48
49 /* Device Parameters Register Map */
50
51 /* DMA Record Register Map */
52
53 /* DMA Arbiter Register Map */
54
55 /* Timer/Counter Register Map */
56 #define GT_TIMER_COUNTER0 0x850
57 #define GT_TIMER_COUNTER1 0x854
58 #define GT_TIMER_COUNTER2 0x858
59 #define GT_TIMER_COUNTER3 0x85c
60
61 #define GT_TIMER_CTRL 0x864
62 #define ENTC0 0x01
63 #define TCSEL0 0x02
64 #define ENTC1 0x04
65 #define TCSEL1 0x08
66 #define ENTC2 0x10
67 #define TCSEL2 0x20
68 #define ENTC3 0x40
69 #define TCSEL3 0x80
70
71 /* PCI Internal Register Map */
72 #define GT_PCI0_CMD_OFS 0xc00
73 #define GT_PCI0_CFG_ADDR 0xcf8
74 #define GT_PCI0_CFG_DATA 0xcfc
75 #define GT_PCI0_INTR_ACK 0xc34
76
77 /* Interrupts Register Map */
78 #define GT_INTR_CAUSE 0xc18
79 #define GTIC_INTSUM 0x00000001
80 #define GTIC_MEMOUT 0x00000002
81 #define GTIC_DMAOUT 0x00000004
82 #define GTIC_CPUOUT 0x00000008
83 #define GTIC_DMA0COMP 0x00000010
84 #define GTIC_DMA1COMP 0x00000020
85 #define GTIC_DMA2COMP 0x00000040
86 #define GTIC_DMA3COMP 0x00000080
87 #define GTIC_T0EXP 0x00000100
88 #define GTIC_T1EXP 0x00000200
89 #define GTIC_T2EXP 0x00000400
90 #define GTIC_T3EXP 0x00000800
91 #define GTIC_MASRDERR0 0x00001000
92 #define GTIC_SLVWRERR0 0x00002000
93 #define GTIC_MASWRERR0 0x00004000
94 #define GTIC_SLVRDERR0 0x00008000
95 #define GTIC_ADDRERR0 0x00010000
96 #define GTIC_MEMERR 0x00020000
97 #define GTIC_MASABORT0 0x00040000
98 #define GTIC_TARABORT0 0x00080000
99 #define GTIC_RETRYCNT0 0x00100000
100 #define GTIC_PMCINT_0 0x00200000
101 #define GTIC_CPUINT 0x0c300000
102 #define GTIC_PCINT 0xc3000000
103 #define GTIC_CPUINTSUM 0x40000000
104 #define GTIC_PCIINTSUM 0x80000000
105
106 /* PCI Configuration Register Map */
107 //#define GT_PCICONFIGBASE 0
108 //#define GT_PCIDID BONITO(GT_PCICONFIGBASE + 0x00)
109 //#define GT_PCICMD BONITO(GT_PCICONFIGBASE + 0x04)
110 //#define GT_PCICLASS BONITO(GT_PCICONFIGBASE + 0x08)
111 //#define GT_PCILTIMER BONITO(GT_PCICONFIGBASE + 0x0c)
112 //#define GT_PCIBASE0 BONITO(GT_PCICONFIGBASE + 0x10)
113 //#define GT_PCIBASE1 BONITO(GT_PCICONFIGBASE + 0x14)
114 //#define GT_PCIBASE2 BONITO(GT_PCICONFIGBASE + 0x18)
115 //#define GT_PCIEXPRBASE BONITO(GT_PCICONFIGBASE + 0x30)
116 //#define GT_PCIINT BONITO(GT_PCICONFIGBASE + 0x3c)
117
118 /* PCI Configuration, Function 1, Register Map */
119
120 /* I2O Support Register Map */
121
122 #endif /* !GTREG_H */

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