/[gxemul]/trunk/src/include/gtreg.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 31 by dpavlin, Mon Oct 8 16:20:40 2007 UTC revision 32 by dpavlin, Mon Oct 8 16:20:58 2007 UTC
# Line 1  Line 1 
1  /*  GXemul: $Id: gtreg.h,v 1.2 2006/08/13 08:34:06 debug Exp $  */  /*  GXemul: $Id: gtreg.h,v 1.3 2006/09/23 03:52:10 debug Exp $  */
2  /*      $NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $  */  /*      $NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $  */
3    
4  /*  /*
5   *  This is basically malta/dev/gtreg.h from NetBSD, with additional   *  This is basically malta/dev/gtreg.h from NetBSD, with additional
6   *  defines that Linux uses. Symbol names are practically the same in   *  defines that Linux uses. Symbol names are practically the same in
7   *  NetBSD and Linux, which simplifies things.   *  NetBSD and Linux, which simplifies things.
8     *
9     *  Also parts from cobalt/dev/gtreg.h from NetBSD.
10     *
11     *  TODO: Find a better gtreg.h.
12   */   */
13    
14  #ifndef GTREG_H  #ifndef GTREG_H
# Line 49  Line 53 
53  /* DMA Arbiter Register Map */  /* DMA Arbiter Register Map */
54    
55  /* Timer/Counter Register Map */  /* Timer/Counter Register Map */
56  //#define       GT_TC_0         0x850  #define GT_TIMER_COUNTER0       0x850
57  //#define       GT_TC_1         0x854  #define GT_TIMER_COUNTER1       0x854
58  //#define       GT_TC_2         0x858  #define GT_TIMER_COUNTER2       0x858
59  //#define       GT_TC_3         0x85c  #define GT_TIMER_COUNTER3       0x85c
60  //#define       GT_TC_CONTROL   0x864  
61    #define GT_TIMER_CTRL           0x864
62    #define  ENTC0                  0x01
63    #define  TCSEL0                 0x02
64    #define  ENTC1                  0x04
65    #define  TCSEL1                 0x08
66    #define  ENTC2                  0x10
67    #define  TCSEL2                 0x20
68    #define  ENTC3                  0x40
69    #define  TCSEL3                 0x80
70    
71  /* PCI Internal Register Map */  /* PCI Internal Register Map */
72  #define GT_PCI0_CMD_OFS         0xc00  #define GT_PCI0_CMD_OFS         0xc00
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