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++ trunk/HISTORY (local) $Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $ 20060626 Continuing on SPARC emulation (beginning on the 'save' instruction, register windows, etc). 20060629 Planning statistics gathering (new -s command line option), and renaming speed_tricks to allow_instruction_combinations. 20060630 Some minor manual page updates. Various cleanups. Implementing the -s command line option. 20060701 FINALLY found the bug which prevented Linux and Ultrix from running without the ugly hack in the R2000/R3000 cache isol code; it was the phystranslation hint array which was buggy. Removing the phystranslation hint code completely, for now. 20060702 Minor dyntrans cleanups; invalidation of physpages now only invalidate those parts of a page that have actually been translated. (32 parts per page.) Some MIPS non-R3000 speed fixes. Experimenting with MIPS instruction combination for some addiu+bne+sw loops, and sw+sw+sw. Adding support (again) for larger-than-4KB pages in MIPS tlbw*. Continuing on SPARC emulation: adding load/store instructions. 20060704 Fixing a virtual vs physical page shift bug in the new tlbw* implementation. Problem noticed by Jakub Jermar. (Many thanks.) Moving rfe and eret to cpu_mips_instr.c, since that is the only place that uses them nowadays. 20060705 Removing the BSD license from the "testmachine" include files, placing them in the public domain instead; this enables the testmachine stuff to be used from projects which are incompatible with the BSD license for some reason. 20060707 Adding instruction combinations for the R2000/R3000 L1 I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu, various branches followed by addiu or nop, and jr ra followed by addiu. The time it takes to perform a full NetBSD/pmax R3000 install on the laptop has dropped from 573 seconds to 539. :-) 20060708 Adding a framebuffer controller device (dev_fbctrl), which so far can be used to change the fb resolution during runtime, but in the future will also be useful for accelerated block fill/ copy, and possibly also simplified character output. Adding an instruction combination for NetBSD/pmax' strlen. 20060709 Minor fixes: reading raw files in src/file.c wasn't memblock aligned, removing buggy multi_sw MIPS instruction combination, etc. 20060711 Adding a machine_qemu.c, which contains a "qemu_mips" machine. (It mimics QEMU's MIPS machine mode, so that a test kernel made for QEMU_MIPS also can run in GXemul... at least to some extent.) Adding a short section about how to run this mode to doc/guestoses.html. 20060714 Misc. minor code cleanups. 20060715 Applying a patch which adds getchar() to promemul/yamon.c (from Oleksandr Tymoshenko). Adding yamon.h from NetBSD, and rewriting yamon.c to use it (instead of ugly hardcoded numbers) + some cleanup. 20060716 Found and fixed the bug which broke single-stepping of 64-bit programs between 0.4.0 and 0.4.0.1 (caused by too quick refactoring and no testing). Hopefully this fix will not break too many other things. 20060718 Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS. Re-adding the sw+sw+sw instr comb (the problem was that I had ignored endian issues); however, it doesn't seem to give any big performance gain. 20060720 Adding a dummy Transputer mode (T414, T800 etc) skeleton (only the 'j' and 'ldc' instructions are implemented so far). :-} 20060721 Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus misc. other updates to get Linux 2.6 for evbmips/malta working (thanks to Alec Voropay for the details). FINALLY found and fixed the bug which made tlbw* for non-R3000 buggy; it was a reference count problem in the dyntrans core. 20060722 Testing stuff; things seem stable enough for a new release. ============== RELEASE 0.4.1 ==============
1 | dpavlin | 28 | /* GXemul: $Id: gtreg.h,v 1.1 2006/07/21 16:55:41 debug Exp $ */ |
2 | /* $NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $ */ | ||
3 | |||
4 | /* | ||
5 | * This is basically malta/dev/gtreg.h from NetBSD, with additional | ||
6 | * defines that Linux uses. Symbol names are practically the same in | ||
7 | * NetBSD and Linux, which simplifies things. | ||
8 | */ | ||
9 | |||
10 | #ifndef GTREG_H | ||
11 | #define GTREG_H | ||
12 | |||
13 | #define GT_REGVAL(x) *((volatile u_int32_t *) \ | ||
14 | (MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x)))) | ||
15 | |||
16 | /* CPU Configuration Register Map */ | ||
17 | #define GT_CPU_INT 0x000 | ||
18 | #define GT_MULTIGT 0x120 | ||
19 | |||
20 | /* CPU Address Decode Register Map */ | ||
21 | #define GT_PCI0IOLD_OFS 0x048 | ||
22 | #define GT_PCI0IOHD_OFS 0x050 | ||
23 | #define GT_PCI0M0LD_OFS 0x058 | ||
24 | #define GT_PCI0M0HD_OFS 0x060 | ||
25 | #define GT_PCI0IOREMAP_OFS 0x0f0 | ||
26 | #define GT_PCI0M0REMAP_OFS 0x0f8 | ||
27 | #define GT_PCI0M1REMAP_OFS 0x100 | ||
28 | |||
29 | /* CPU Error Report Register Map */ | ||
30 | |||
31 | /* CPU Sync Barrier Register Map */ | ||
32 | |||
33 | /* SDRAM and Device Address Decode Register Map */ | ||
34 | |||
35 | /* SDRAM Configuration Register Map */ | ||
36 | |||
37 | /* SDRAM Parameters Register Map */ | ||
38 | |||
39 | /* ECC Register Map */ | ||
40 | |||
41 | /* Device Parameters Register Map */ | ||
42 | |||
43 | /* DMA Record Register Map */ | ||
44 | |||
45 | /* DMA Arbiter Register Map */ | ||
46 | |||
47 | /* Timer/Counter Register Map */ | ||
48 | //#define GT_TC_0 0x850 | ||
49 | //#define GT_TC_1 0x854 | ||
50 | //#define GT_TC_2 0x858 | ||
51 | //#define GT_TC_3 0x85c | ||
52 | //#define GT_TC_CONTROL 0x864 | ||
53 | |||
54 | /* PCI Internal Register Map */ | ||
55 | #define GT_PCI0_CMD_OFS 0xc00 | ||
56 | #define GT_PCI0_CFG_ADDR 0xcf8 | ||
57 | #define GT_PCI0_CFG_DATA 0xcfc | ||
58 | #define GT_PCI0_INTR_ACK 0xc34 | ||
59 | |||
60 | /* Interrupts Register Map */ | ||
61 | #define GT_INTR_CAUSE 0xc18 | ||
62 | #define GTIC_INTSUM 0x00000001 | ||
63 | #define GTIC_MEMOUT 0x00000002 | ||
64 | #define GTIC_DMAOUT 0x00000004 | ||
65 | #define GTIC_CPUOUT 0x00000008 | ||
66 | #define GTIC_DMA0COMP 0x00000010 | ||
67 | #define GTIC_DMA1COMP 0x00000020 | ||
68 | #define GTIC_DMA2COMP 0x00000040 | ||
69 | #define GTIC_DMA3COMP 0x00000080 | ||
70 | #define GTIC_T0EXP 0x00000100 | ||
71 | #define GTIC_T1EXP 0x00000200 | ||
72 | #define GTIC_T2EXP 0x00000400 | ||
73 | #define GTIC_T3EXP 0x00000800 | ||
74 | #define GTIC_MASRDERR0 0x00001000 | ||
75 | #define GTIC_SLVWRERR0 0x00002000 | ||
76 | #define GTIC_MASWRERR0 0x00004000 | ||
77 | #define GTIC_SLVRDERR0 0x00008000 | ||
78 | #define GTIC_ADDRERR0 0x00010000 | ||
79 | #define GTIC_MEMERR 0x00020000 | ||
80 | #define GTIC_MASABORT0 0x00040000 | ||
81 | #define GTIC_TARABORT0 0x00080000 | ||
82 | #define GTIC_RETRYCNT0 0x00100000 | ||
83 | #define GTIC_PMCINT_0 0x00200000 | ||
84 | #define GTIC_CPUINT 0x0c300000 | ||
85 | #define GTIC_PCINT 0xc3000000 | ||
86 | #define GTIC_CPUINTSUM 0x40000000 | ||
87 | #define GTIC_PCIINTSUM 0x80000000 | ||
88 | |||
89 | /* PCI Configuration Register Map */ | ||
90 | //#define GT_PCICONFIGBASE 0 | ||
91 | //#define GT_PCIDID BONITO(GT_PCICONFIGBASE + 0x00) | ||
92 | //#define GT_PCICMD BONITO(GT_PCICONFIGBASE + 0x04) | ||
93 | //#define GT_PCICLASS BONITO(GT_PCICONFIGBASE + 0x08) | ||
94 | //#define GT_PCILTIMER BONITO(GT_PCICONFIGBASE + 0x0c) | ||
95 | //#define GT_PCIBASE0 BONITO(GT_PCICONFIGBASE + 0x10) | ||
96 | //#define GT_PCIBASE1 BONITO(GT_PCICONFIGBASE + 0x14) | ||
97 | //#define GT_PCIBASE2 BONITO(GT_PCICONFIGBASE + 0x18) | ||
98 | //#define GT_PCIEXPRBASE BONITO(GT_PCICONFIGBASE + 0x30) | ||
99 | //#define GT_PCIINT BONITO(GT_PCICONFIGBASE + 0x3c) | ||
100 | |||
101 | /* PCI Configuration, Function 1, Register Map */ | ||
102 | |||
103 | /* I2O Support Register Map */ | ||
104 | |||
105 | #endif /* !GTREG_H */ |
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