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Revision Log
++ trunk/HISTORY (local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816 Adding a framework for emulated/virtual timers (src/timer.c),
using only setitimer().
Rewriting the mc146818 to use the new timer framework.
20060817 Adding a call to gettimeofday() every now and then (once every
second, at the moment) to resynch the timer if it drifts.
Beginning to convert the ISA timer interrupt mechanism (8253
and 8259) to use the new timer framework.
Removing the -I command line option.
20060819 Adding the -I command line option again, with new semantics.
Working on Footbridge timer interrupts; NetBSD/NetWinder and
NetBSD/CATS now run at correct speed, but unfortunately with
HUGE delays during bootup.
20060821 Some minor m68k updates. Adding the first instruction: nop. :)
Minor Alpha emulation updates.
20060822 Adding a FreeBSD development specific YAMON environment
variable ("khz") (as suggested by Bruce M. Simpson).
Moving YAMON environment variable initialization from
machine_evbmips.c into promemul/yamon.c, and adding some more
variables.
Continuing on the LCA PCI bus controller (for Alpha machines).
20060823 Continuing on the timer stuff: experimenting with MIPS count/
compare interrupts connected to the timer framework.
20060825 Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
Minor updates to the LCA PCI controller.
20060827 Implementing a CHIP8 cpu mode, and a corresponding CHIP8
machine, for fun. Disassembly support for all instructions,
and most of the common instructions have been implemented: mvi,
mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828 Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
(more correct) RCA 180x cpu. (Disassembly for all 1802
instructions has been implemented, but no execution yet, and
no 1805 extended instructions.)
20060829 Minor Alpha emulation updates.
20060830 Beginning to experiment a little with PCI IDE for SGI O2.
Fixing the cursor key mappings for MobilePro 770 emulation.
Fixing the LK201 warning caused by recent NetBSD/pmax.
The MIPS R41xx standby, suspend, and hibernate instructions now
behave like the RM52xx/MIPS32/MIPS64 wait instruction.
Fixing dev_wdc so it calculates correct (64-bit) offsets before
giving them to diskimage_access().
20060831 Continuing on Alpha emulation (OSF1 PALcode).
20060901 Minor Alpha updates; beginning on virtual memory pagetables.
Removed the limit for max nr of devices (in preparation for
allowing devices' base addresses to be changed during runtime).
Adding a hack for MIPS [d]mfc0 select 0 (except the count
register), so that the coproc register is simply copied.
The MIPS suspend instruction now exits the emulator, instead
of being treated as a wait instruction (this causes NetBSD/
hpcmips to get correct 'halt' behavior).
The VR41xx RTC now returns correct time.
Connecting the VR41xx timer to the timer framework (fixed at
128 Hz, for now).
Continuing on SPARC emulation, adding more instructions:
restore, ba_xcc, ble. The rectangle drawing demo works :)
Removing the last traces of the old ENABLE_CACHE_EMULATION
MIPS stuff (not usable with dyntrans anyway).
20060902 Splitting up src/net.c into several smaller files in its own
subdirectory (src/net/).
20060903 Cleanup of the files in src/net/, to make them less ugly.
20060904 Continuing on the 'settings' subsystem.
Minor progress on the SPARC emulation mode.
20060905 Cleanup of various things, and connecting the settings
infrastructure to various subsystems (emul, machine, cpu, etc).
Changing the lk201 mouse update routine to not rely on any
emulated hardware framebuffer cursor coordinates, but instead
always do (semi-usable) relative movements.
20060906 Continuing on the lk201 mouse stuff. Mouse behaviour with
multiple framebuffers (which was working in Ultrix) is now
semi-broken (but it still works, in a way).
Moving the documentation about networking into its own file
(networking.html), and refreshing it a bit. Adding an example
of how to use ethernet frame direct-access (udp_snoop).
20060907 Continuing on the settings infrastructure.
20060908 Minor updates to SH emulation: for 32-bit emulation: delay
slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
ice, for now.
20060909-10 Implementing some more 32-bit SH instructions. Removing the
64-bit mode completely. Enough has now been implemented to run
the rectangle drawing demo. :-)
20060912 Adding more SH instructions.
20060916 Continuing on SH emulation (some more instructions: div0u,
div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
Continuing on the settings subsystem (beginning on reading/
writing settings, removing bugs, and connecting more cpus to
the framework).
20060919 More work on SH emulation; adding an ldc banked instruction,
and attaching a 640x480 framebuffer to the Dreamcast machine
mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
and then panics).
20060920 Continuing on the settings subsystem.
20060921 Fixing the Footbridge timer stuff so that NetBSD/cats and
NetBSD/netwinder boot up without the delays.
20060922 Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
'wait' support disabled, NetBSD/malta and Linux/malta run at
correct speed.
20060923 Connecting dev_gt to the timer framework, so that NetBSD/cobalt
runs at correct speed.
Moving SH4-specific memory mapped registers into its own
device (dev_sh4.c).
Running with -N now prints "idling" instead of bogus nr of
instrs/second (which isn't valid anyway) while idling.
20060924 Algor emulation should now run at correct speed.
Adding disassembly support for some MIPS64 revision 2
instructions: ext, dext, dextm, dextu.
20060926 The timer framework now works also when the MIPS wait
instruction is used.
20060928 Re-implementing checks for coprocessor availability for MIPS
cop0 instructions. (Thanks to Carl van Schaik for noticing the
lack of cop0 availability checks.)
20060929 Implementing an instruction combination hack which treats
NetBSD/pmax' idle loop as a wait-like instruction.
20060930 The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
causing TLB lookups to sometimes succeed when they should have
failed. (A big thank you to Juli Mallett for noticing the
problem.)
Adding disassembly support for more MIPS64 revision 2 opcodes
(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
implementing seb, seh, dsbh, dshd, and wsbh.
Implementing an instruction combination hack for Linux/pmax'
idle loop, similar to the NetBSD/pmax case.
20061001 Changing the NetBSD/sgimips install instructions to extract
files from an iso image, instead of downloading them via ftp.
20061002 More-than-31-bit userland addresses in memory_mips_v2p.c were
not actually working; applying a fix from Carl van Schaik to
enable them to work + making some other updates (adding kuseg
support).
Fixing hpcmips (vr41xx) timer initialization.
Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
loop. Seems to work both for R3000 and non-R3000.
20061003 Continuing a little on SH emulation (adding more control
registers; mini-cleanup of memory_sh.c).
20061004 Beginning on a dev_rtc, a clock/timer device for the test
machines; also adding a demo, and some documentation.
Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
sign-extended), and adding the addc and ldtlb instructions.
20061005 Contining on SH emulation: virtual to physical address
translation, and a skeleton exception mechanism.
20061006 Adding more SH instructions (various loads and stores, rte,
negc, muls.w, various privileged register-move instructions).
20061007 More SH instructions: various move instructions, trapa, div0s,
float, fdiv, ftrc.
Continuing on dev_rtc; removing the rtc demo.
20061008 Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
programs using KOS libs need this.)
Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
fmul, fadd, various floating-point moves, etc. A 256-byte
demo for Dreamcast runs :-)
20061012 Adding the SH "lds Rm,pr" and bsr instructions.
20061013 More SH instructions: "sts fpscr,rn", tas.b, and some more
floating point instructions, cmp/str, and more moves.
Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014 Generalizing the expression evaluator (used in the built-in
debugger) to support parentheses and +-*/%^&|.
20061015 Removing the experimental tlb index hint code in
mips_memory_v2p.c, since it didn't really have any effect.
20061017 Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
frchg, and some other instructions. Fixing missing sign-
extension in an 8-bit load instruction.
20061019 Adding a simple dev_dreamcast_rtc.
Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021 Continuing on various SH and Dreamcast things: sh4 timers,
debug messages for dev_pvr, fixing some virtual address
translation bugs, adding the bsrf instruction.
The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
Adding a dummy dev_dreamcast_asic.c (not really useful yet).
Implementing simple support for Store Queues.
Beginning on the PVR Tile Accelerator.
20061022 Generalizing the PVR framebuffer to support off-screen drawing,
multiple bit-depths, etc. (A small speed penalty, but most
likely worth it.)
Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
fschg, and some more); correcting bugs in "fsca" and "float".
20061024 Adding the SH ftrv (matrix * vector) instruction. Marcus
Comstedt's "tatest" example runs :) (wireframe only).
Correcting disassembly for SH floating point instructions that
use the xd* registers.
Adding the SH fsts instruction.
In memory_device_dyntrans_access(), only the currently used
range is now invalidated, and not the entire device range.
20061025 Adding a dummy AVR32 cpu mode skeleton.
20061026 Various Dreamcast updates; beginning on a Maple bus controller.
20061027 Continuing on the Maple bus. A bogus Controller, Keyboard, and
Mouse can now be detected by NetBSD and KOS homebrew programs.
Cleaning up the SH4 Timer Management Unit, and beginning on
SH4 interrupts.
Implementing the Dreamcast SYSASIC.
20061028 Continuing on the SYSASIC.
Adding the SH fsqrt instruction.
memory_sh.c now actually scans the ITLB.
Fixing a bug in dev_sh4.c, related to associative writes into
the memory-mapped UTLB array. NetBSD/dreamcast now reaches
userland stably, and prints the "Terminal type?" message :-]
Implementing enough of the Dreamcast keyboard to make NetBSD
accept it for input.
Enabling SuperH for stable (non-development) builds.
Adding NetBSD/dreamcast to the documentation, although it
doesn't support root-on-nfs yet.
20061029 Changing usleep(1) calls in the debugger to to usleep(10000)
(according to Brian Foley, this makes GXemul run better on
MacOS X).
Making the Maple "Controller" do something (enough to barely
interact with dcircus.elf).
20061030-31 Some progress on the PVR. More test programs start running (but
with strange output).
Various other SH4-related updates.
20061102 Various Dreamcast and SH4 updates; more KOS demos run now.
20061104 Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105 Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
Testing for the release.
============== RELEASE 0.4.3 ==============
| 1 | /* GXemul: $Id: dreamcast_pvr.h,v 1.6 2006/10/31 08:27:26 debug Exp $ */ |
| 2 | /* $NetBSD: pvr.c,v 1.22 2006/04/12 19:38:22 jmmv Exp $ */ |
| 3 | |
| 4 | #ifndef DREAMCAST_PVR_H |
| 5 | #define DREAMCAST_PVR_H |
| 6 | |
| 7 | /* |
| 8 | * Note: This was pvr.c in NetBSD. It has been extended with reasonably |
| 9 | * similar symbolnames from http://www.ludd.luth.se/~jlo/dc/powervr-reg.txt. |
| 10 | * |
| 11 | * There are still many things missing. |
| 12 | */ |
| 13 | |
| 14 | /*- |
| 15 | * Copyright (c) 2001 Marcus Comstedt. |
| 16 | * Copyright (c) 2001 Jason R. Thorpe. |
| 17 | * All rights reserved. |
| 18 | * |
| 19 | * Redistribution and use in source and binary forms, with or without |
| 20 | * modification, are permitted provided that the following conditions |
| 21 | * are met: |
| 22 | * 1. Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * 2. Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * 3. All advertising materials mentioning features or use of this software |
| 28 | * must display the following acknowledgement: |
| 29 | * This product includes software developed by Marcus Comstedt. |
| 30 | * 4. Neither the name of The NetBSD Foundation nor the names of its |
| 31 | * contributors may be used to endorse or promote products derived |
| 32 | * from this software without specific prior written permission. |
| 33 | * |
| 34 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 35 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 36 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 37 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 38 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 39 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 40 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 41 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 42 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 43 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 44 | * POSSIBILITY OF SUCH DAMAGE. |
| 45 | */ |
| 46 | |
| 47 | /* |
| 48 | * Copyright (c) 1998, 1999 Tohru Nishimura. All rights reserved. |
| 49 | * |
| 50 | * Redistribution and use in source and binary forms, with or without |
| 51 | * modification, are permitted provided that the following conditions |
| 52 | * are met: |
| 53 | * 1. Redistributions of source code must retain the above copyright |
| 54 | * notice, this list of conditions and the following disclaimer. |
| 55 | * 2. Redistributions in binary form must reproduce the above copyright |
| 56 | * notice, this list of conditions and the following disclaimer in the |
| 57 | * documentation and/or other materials provided with the distribution. |
| 58 | * 3. All advertising materials mentioning features or use of this software |
| 59 | * must display the following acknowledgement: |
| 60 | * This product includes software developed by Tohru Nishimura |
| 61 | * for the NetBSD Project. |
| 62 | * 4. The name of the author may not be used to endorse or promote products |
| 63 | * derived from this software without specific prior written permission |
| 64 | * |
| 65 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 66 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 67 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 68 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 69 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 70 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 71 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 72 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 73 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 74 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 75 | */ |
| 76 | |
| 77 | #define PVRREG_FBSTART 0x05000000 |
| 78 | #define PVRREG_REGSTART 0x005f8000 |
| 79 | |
| 80 | #define PVRREG_REGSIZE 0x00002000 |
| 81 | |
| 82 | |
| 83 | #define PVRREG_ID 0x00 |
| 84 | |
| 85 | #define PVRREG_REVISION 0x04 |
| 86 | #define PVR_REVISION_MINOR_MASK 0xf |
| 87 | #define PVR_REVISION_MAJOR_MASK 0xf0 |
| 88 | #define PVR_REVISION_MAJOR_SHIFT 4 |
| 89 | |
| 90 | #define PVRREG_RESET 0x08 |
| 91 | #define PVR_RESET_TA 0x00000001 |
| 92 | #define PVR_RESET_PVR 0x00000002 |
| 93 | #define PVR_RESET_BUS 0x00000004 |
| 94 | |
| 95 | #define PVRREG_STARTRENDER 0x14 |
| 96 | |
| 97 | #define PVRREG_OB_ADDR 0x20 |
| 98 | /* Object Buffer start address. Bits 0..19 should always be zero. */ |
| 99 | #define PVR_OB_ADDR_MASK 0x00f00000 |
| 100 | |
| 101 | #define PVRREG_TILEBUF_ADDR 0x2c |
| 102 | #define PVR_TILEBUF_ADDR_MASK 0x00fffff8 |
| 103 | |
| 104 | #define PVRREG_SPANSORT 0x30 |
| 105 | #define PVR_SPANSORT_SPAN0 0x00000001 |
| 106 | #define PVR_SPANSORT_SPAN1 0x00000100 |
| 107 | #define PVR_SPANSORT_TSP_CACHE_ENABLE 0x00010000 |
| 108 | |
| 109 | #define PVRREG_BRDCOLR 0x40 |
| 110 | #define BRDCOLR_BLUE(x) ((x) << 0) |
| 111 | #define BRDCOLR_GREEN(x) ((x) << 8) |
| 112 | #define BRDCOLR_RED(x) ((x) << 16) |
| 113 | |
| 114 | #define PVRREG_DIWMODE 0x44 |
| 115 | #define DIWMODE_DE (1U << 0) /* display enable */ |
| 116 | #define DIWMODE_SD (1U << 1) /* scan double enable */ |
| 117 | #define DIWMODE_COL(x) ((x) << 2) |
| 118 | #define DIWMODE_COL_RGB555 DIWMODE_COL(0) /* RGB555, 16-bit */ |
| 119 | #define DIWMODE_COL_RGB565 DIWMODE_COL(1) /* RGB565, 16-bit */ |
| 120 | #define DIWMODE_COL_RGB888 DIWMODE_COL(2) /* RGB888, 24-bit */ |
| 121 | #define DIWMODE_COL_ARGB888 DIWMODE_COL(3) /* RGB888, 32-bit */ |
| 122 | #define DIWMODE_C (1U << 23) /* 2x clock enable (VGA) */ |
| 123 | #define DIWMODE_DE_MASK 0x00000001 |
| 124 | #define DIWMODE_SD_MASK 0x00000002 /* Line double */ |
| 125 | #define DIWMODE_COL_MASK 0x0000000c /* Pixel mode */ |
| 126 | #define DIWMODE_COL_SHIFT 2 |
| 127 | #define DIWMODE_EX_MASK 0x00000070 /* Extend bits */ |
| 128 | #define DIWMODE_EX_SHIFT 4 |
| 129 | #define DIWMODE_TH_MASK 0x0000ff00 /* ARGB8888 threshold */ |
| 130 | #define DIWMODE_TH_SHIFT 8 |
| 131 | #define DIWMODE_SL_MASK 0x003f0000 /* Strip Length */ |
| 132 | #define DIWMODE_SL_SHIFT 16 |
| 133 | #define DIWMODE_SE_MASK 0x00400000 /* Strip Buffer enabled */ |
| 134 | #define DIWMODE_C_MASK 0x00800000 /* Clock double */ |
| 135 | |
| 136 | #define PVRREG_FB_RENDER_CFG 0x48 |
| 137 | /* TODO */ |
| 138 | |
| 139 | #define PVRREG_FB_RENDER_MODULO 0x4c |
| 140 | #define FB_RENDER_MODULO_MASK 0x000001ff |
| 141 | /* TODO */ |
| 142 | |
| 143 | #define PVRREG_DIWADDRL 0x50 |
| 144 | |
| 145 | #define PVRREG_DIWADDRS 0x54 |
| 146 | |
| 147 | #define PVRREG_DIWSIZE 0x5c |
| 148 | #define DIWSIZE_DPL(x) ((x) << 0) /* pixel data per line */ |
| 149 | #define DIWSIZE_LPF(x) ((x) << 10) /* lines per field */ |
| 150 | #define DIWSIZE_MODULO(x) ((x) << 20) /* words to skip + 1 */ |
| 151 | #define DIWSIZE_MASK 0x3ff /* All fields are 10 bits. */ |
| 152 | #define DIWSIZE_DPL_SHIFT 0 |
| 153 | #define DIWSIZE_LPF_SHIFT 10 |
| 154 | #define DIWSIZE_MODULO_SHIFT 20 |
| 155 | |
| 156 | #define PVRREG_FB_RENDER_ADDR1 0x60 /* Odd interlace lines */ |
| 157 | |
| 158 | #define PVRREG_FB_RENDER_ADDR2 0x64 /* Even interlace lines */ |
| 159 | |
| 160 | #define PVRREG_VRAM_CFG1 0xa0 |
| 161 | #define VRAM_CFG1_GOOD_REFRESH_VALUE 0x20 |
| 162 | |
| 163 | #define PVRREG_VRAM_CFG2 0xa4 |
| 164 | #define VRAM_CFG2_UNKNOWN_MAGIC 0x0000001f |
| 165 | |
| 166 | #define PVRREG_VRAM_CFG3 0xa8 |
| 167 | #define VRAM_CFG3_UNKNOWN_MAGIC 0x15d1c951 |
| 168 | |
| 169 | #define PVRREG_FOG_TABLE_COL 0xb0 |
| 170 | |
| 171 | #define PVRREG_FOG_VERTEX_COL 0xb4 |
| 172 | |
| 173 | #define PVRREG_RASEVTPOS 0xcc |
| 174 | #define RASEVTPOS_POS2_MASK 0x000003ff |
| 175 | #define RASEVTPOS_POS1_MASK 0x03ff0000 |
| 176 | #define RASEVTPOS_POS1_SHIFT 16 |
| 177 | #define RASEVTPOS_BOTTOM(x) ((x) << 0) |
| 178 | #define RASEVTPOS_TOP(x) ((x) << 16) |
| 179 | |
| 180 | #define PVRREG_SYNCCONF 0xd0 |
| 181 | #define SYNCCONF_VP (1U << 0) /* V-sync polarity */ |
| 182 | #define SYNCCONF_HP (1U << 1) /* H-sync polarity */ |
| 183 | #define SYNCCONF_I (1U << 4) /* interlace */ |
| 184 | #define SYNCCONF_BC(x) (1U << 6) /* broadcast standard */ |
| 185 | #define SYNCCONF_VO (1U << 8) /* video output enable */ |
| 186 | #define SYNCCONF_VO_MASK 0x00000100 |
| 187 | #define SYNCCONF_BC_MASK 0x000000c0 |
| 188 | #define SYNCCONF_BC_SHIFT 6 |
| 189 | #define SYNCCONF_BC_VGA 0 |
| 190 | #define SYNCCONF_BC_NTSC 1 |
| 191 | #define SYNCCONF_BC_PAL 2 |
| 192 | #define SYNCCONF_I_MASK 0x00000010 |
| 193 | #define SYNCCONF_HP_MASK 0x00000004 /* Positive H-sync */ |
| 194 | #define SYNCCONF_VP_MASK 0x00000002 /* Positive V-sync */ |
| 195 | |
| 196 | #define PVRREG_BRDHORZ 0xd4 |
| 197 | #define BRDHORZ_STOP_MASK 0x0000ffff |
| 198 | #define BRDHORZ_START_MASK 0xffff0000 |
| 199 | #define BRDHORZ_START_SHIFT 16 |
| 200 | #define BRDHORZ_STOP(x) ((x) << 0) |
| 201 | #define BRDHORZ_START(x) ((x) << 16) |
| 202 | |
| 203 | #define PVRREG_SYNCSIZE 0xd8 |
| 204 | #define SYNCSIZE_H_MASK 0x0000ffff |
| 205 | #define SYNCSIZE_V_MASK 0xffff0000 |
| 206 | #define SYNCSIZE_V_SHIFT 16 |
| 207 | #define SYNCSIZE_H(x) ((x) << 0) |
| 208 | #define SYNCSIZE_V(x) ((x) << 16) |
| 209 | |
| 210 | #define PVRREG_BRDVERT 0xdc |
| 211 | #define BRDVERT_STOP_MASK 0x0000ffff |
| 212 | #define BRDVERT_START_MASK 0xffff0000 |
| 213 | #define BRDVERT_START_SHIFT 16 |
| 214 | #define BRDVERT_STOP(x) ((x) << 0) |
| 215 | #define BRDVERT_START(x) ((x) << 16) |
| 216 | |
| 217 | #define PVRREG_DIWCONF 0xe8 |
| 218 | #define DIWCONF_BLANK (1U << 3) /* blank screen */ |
| 219 | #define DIWCONF_LR (1U << 8) /* low-res (320 horizontal) */ |
| 220 | #define DIWCONF_MAGIC_MASK 0x003f0000 |
| 221 | #define DIWCONF_MAGIC (22 << 16) |
| 222 | |
| 223 | #define PVRREG_DIWHSTRT 0xec |
| 224 | #define DIWVSTRT_HPOS_MASK 0x000003ff |
| 225 | |
| 226 | #define PVRREG_DIWVSTRT 0xf0 |
| 227 | #define DIWVSTRT_V1_MASK 0x000003ff |
| 228 | #define DIWVSTRT_V2_MASK 0x03ff0000 |
| 229 | #define DIWVSTRT_V2_SHIFT 16 |
| 230 | #define DIWVSTRT_V1(x) ((x) << 0) |
| 231 | #define DIWVSTRT_V2(x) ((x) << 16) |
| 232 | |
| 233 | #define PVRREG_PALETTE_CFG 0x108 |
| 234 | #define PVR_PALETTE_CFG_MODE_MASK 0x3 |
| 235 | #define PVR_PALETTE_CFG_MODE_ARGB1555 0x0 |
| 236 | #define PVR_PALETTE_CFG_MODE_RGB565 0x1 |
| 237 | #define PVR_PALETTE_CFG_MODE_ARGB4444 0x2 |
| 238 | #define PVR_PALETTE_CFG_MODE_ARGB8888 0x3 |
| 239 | |
| 240 | #define PVRREG_SYNC_STAT 0x10c |
| 241 | #define PVR_SYNC_STAT_VPOS_MASK 0x000003ff |
| 242 | #define PVR_SYNC_STAT_INTERLACE_FIELD_EVEN 0x00000400 |
| 243 | #define PVR_SYNC_STAT_HBLANK 0x00001000 |
| 244 | #define PVR_SYNC_STAT_VBLANK 0x00002000 |
| 245 | |
| 246 | #define PVRREG_TA_OPB_START 0x124 |
| 247 | #define TA_OPB_START_MASK 0x00ffff80 |
| 248 | |
| 249 | #define PVRREG_TA_OB_START 0x128 |
| 250 | #define TA_OB_START_MASK 0x00fffff8 |
| 251 | |
| 252 | #define PVRREG_TA_OPB_END 0x12c |
| 253 | #define TA_OPB_END_MASK 0x00ffff80 |
| 254 | |
| 255 | #define PVRREG_TA_OB_END 0x130 |
| 256 | #define TA_OB_END_MASK 0x00fffff8 |
| 257 | |
| 258 | #define PVRREG_TA_OPB_POS 0x134 |
| 259 | #define TA_OPB_POS_MASK 0x00ffff80 |
| 260 | |
| 261 | #define PVRREG_TA_OB_POS 0x138 |
| 262 | #define TA_OB_POS_MASK 0x00fffff8 |
| 263 | |
| 264 | #define PVRREG_TILEBUF_SIZE 0x13c |
| 265 | #define TILEBUF_SIZE_HEIGHT_MASK 0xffff0000 |
| 266 | #define TILEBUF_SIZE_HEIGHT_SHIFT 16 |
| 267 | #define TILEBUF_SIZE_WIDTH_MASK 0x0000ffff |
| 268 | |
| 269 | #define PVRREG_TA_OPB_CFG 0x140 |
| 270 | #define TA_OPB_CFG_OPAQUEPOLY_MASK 0x00000003 |
| 271 | #define TA_OPB_CFG_OPAQUEMOD_MASK 0x00000030 |
| 272 | #define TA_OPB_CFG_OPAQUEMOD_SHIFT 4 |
| 273 | #define TA_OPB_CFG_TRANSPOLY_MASK 0x00000300 |
| 274 | #define TA_OPB_CFG_TRANSPOLY_SHIFT 8 |
| 275 | #define TA_OPB_CFG_TRANSMOD_MASK 0x00003000 |
| 276 | #define TA_OPB_CFG_TRANSMOD_SHIFT 12 |
| 277 | #define TA_OPB_CFG_PUNCHTHROUGH_MASK 0x00030000 |
| 278 | #define TA_OPB_CFG_PUNCHTHROUGH_SHIFT 16 |
| 279 | #define TA_OPB_CFG_OPBDIR 0x00100000 |
| 280 | |
| 281 | #define PVRREG_TA_INIT 0x144 |
| 282 | #define PVR_TA_INIT 0x80000000 |
| 283 | |
| 284 | #define PVRREG_YUV_ADDR 0x148 |
| 285 | #define PVR_YUV_ADDR_MASK 0x00ffffe0 |
| 286 | |
| 287 | #define PVRREG_YUV_CFG1 0x14c |
| 288 | /* TODO */ |
| 289 | |
| 290 | #define PVRREG_YUV_STAT 0x150 |
| 291 | /* Nr of currently converted 16x16 macro blocks. */ |
| 292 | #define PVR_YUV_STAT_BLOCKS_MASK 0x1fff |
| 293 | |
| 294 | #define PVRREG_TA_OPL_REINIT 0x160 |
| 295 | #define PVR_TA_OPL_REINIT 0x80000000 |
| 296 | |
| 297 | #define PVRREG_TA_OPL_INIT 0x164 |
| 298 | /* Start of Object Pointer List allocation in VRAM. */ |
| 299 | #define PVR_TA_OPL_INIT_MASK 0x00ffff80 |
| 300 | |
| 301 | #define PVRREG_FOG_TABLE 0x0200 |
| 302 | #define PVR_FOG_TABLE_SIZE 0x0200 |
| 303 | |
| 304 | #define PVRREG_PALETTE 0x1000 |
| 305 | #define PVR_PALETTE_SIZE 0x1000 |
| 306 | |
| 307 | #endif /* DREAMCAST_PVR_H */ |
| 308 |
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