/[gxemul]/trunk/src/include/dp83932reg.h
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Annotation of /trunk/src/include/dp83932reg.h

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Revision 4 - (hide annotations)
Mon Oct 8 16:18:00 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 11982 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============
1 dpavlin 4 /* gxemul: $Id: dp83932reg.h,v 1.3 2005/03/05 12:34:02 debug Exp $ */
2     /* $NetBSD: dp83932reg.h,v 1.2 2002/05/03 00:07:02 thorpej Exp $ */
3    
4     #ifndef _DEV_IC_DP83932REG_H_
5     #define _DEV_IC_DP83932REG_H_
6    
7     #ifdef __attribute__
8     #undef __attribute__
9     #endif
10    
11     #ifdef __noreturn__
12     #undef __noreturn__
13     #endif
14    
15     #define __attribute__(x) /* */
16     #define __noreturn__ /* */
17    
18     /*-
19     * Copyright (c) 2001 The NetBSD Foundation, Inc.
20     * All rights reserved.
21     *
22     * This code is derived from software contributed to The NetBSD Foundation
23     * by Jason R. Thorpe.
24     *
25     * Redistribution and use in source and binary forms, with or without
26     * modification, are permitted provided that the following conditions
27     * are met:
28     * 1. Redistributions of source code must retain the above copyright
29     * notice, this list of conditions and the following disclaimer.
30     * 2. Redistributions in binary form must reproduce the above copyright
31     * notice, this list of conditions and the following disclaimer in the
32     * documentation and/or other materials provided with the distribution.
33     * 3. All advertising materials mentioning features or use of this software
34     * must display the following acknowledgement:
35     * This product includes software developed by the NetBSD
36     * Foundation, Inc. and its contributors.
37     * 4. Neither the name of The NetBSD Foundation nor the names of its
38     * contributors may be used to endorse or promote products derived
39     * from this software without specific prior written permission.
40     *
41     * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
42     * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
43     * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
44     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
45     * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
46     * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
47     * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
48     * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
49     * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
50     * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
51     * POSSIBILITY OF SUCH DAMAGE.
52     */
53    
54     /*
55     * Register description for the National Semiconductor DP83932
56     * Systems-Oriented Network Interface Controller (SONIC).
57     */
58    
59     /*
60     * SONIC Receive Descriptor Area.
61     */
62     struct sonic_rda16 {
63     uint16_t rda_status;
64     uint16_t rda_bytecount;
65     uint16_t rda_pkt_ptr0;
66     uint16_t rda_pkt_ptr1;
67     uint16_t rda_seqno;
68     uint16_t rda_link;
69     uint16_t rda_inuse;
70     } __attribute__((__packed__));
71    
72     struct sonic_rda32 {
73     uint32_t rda_status;
74     uint32_t rda_bytecount;
75     uint32_t rda_pkt_ptr0;
76     uint32_t rda_pkt_ptr1;
77     uint32_t rda_seqno;
78     uint32_t rda_link;
79     uint32_t rda_inuse;
80     } __attribute__((__packed__));
81    
82     #define RDA_SEQNO_RBA(x) (((x) >> 8) & 0xff)
83     #define RDA_SEQNO_RSN(x) ((x) & 0xff)
84    
85     #define RDA_LINK_EOL 0x01 /* end-of-list */
86    
87     /*
88     * SONIC Receive Resource Area.
89     *
90     * Note, in 32-bit mode, Rx buffers must be aligned to 32-bit
91     * boundaries, and in 16-bit mode, to 16-bit boundaries.
92     *
93     * Also note the `word count' is always in units of 16-bit words.
94     */
95     struct sonic_rra16 {
96     uint16_t rra_ptr0;
97     uint16_t rra_ptr1;
98     uint16_t rra_wc0;
99     uint16_t rra_wc1;
100     } __attribute__((__packed__));
101    
102     struct sonic_rra32 {
103     uint32_t rra_ptr0;
104     uint32_t rra_ptr1;
105     uint32_t rra_wc0;
106     uint32_t rra_wc1;
107     } __attribute__((__packed__));
108    
109     /*
110     * SONIC Transmit Descriptor Area
111     *
112     * Note the number of fragments defined here is arbitrary.
113     */
114     #define SONIC_NTXFRAGS 16
115    
116     struct sonic_frag16 {
117     uint16_t frag_ptr0;
118     uint16_t frag_ptr1;
119     uint16_t frag_size;
120     } __attribute__((__packed__));
121    
122     struct sonic_frag32 {
123     uint32_t frag_ptr0;
124     uint32_t frag_ptr1;
125     uint32_t frag_size;
126     } __attribute__((__packed__));
127    
128     /*
129     * Note the frag after the last frag is used to link up to the
130     * next descriptor.
131     */
132    
133     struct sonic_tda16 {
134     uint16_t tda_status;
135     uint16_t tda_pktconfig;
136     uint16_t tda_pktsize;
137     uint16_t tda_fragcnt;
138     struct sonic_frag16 tda_frags[SONIC_NTXFRAGS + 1];
139     #if 0
140     uint16_t tda_link;
141     #endif
142     } __attribute__((__packed__));
143    
144     struct sonic_tda32 {
145     uint32_t tda_status;
146     uint32_t tda_pktconfig;
147     uint32_t tda_pktsize;
148     uint32_t tda_fragcnt;
149     struct sonic_frag32 tda_frags[SONIC_NTXFRAGS + 1];
150     #if 0
151     uint32_t tda_link;
152     #endif
153     } __attribute__((__packed__));
154    
155     #define TDA_STATUS_NCOL(x) (((x) >> 11) & 0x1f)
156    
157     #define TDA_LINK_EOL 0x01 /* end-of-list */
158    
159     /*
160     * SONIC CAM Descriptor Area.
161     */
162     struct sonic_cda16 {
163     uint16_t cda_entry;
164     uint16_t cda_addr0;
165     uint16_t cda_addr1;
166     uint16_t cda_addr2;
167     } __attribute__((__packed__));
168    
169     struct sonic_cda32 {
170     uint32_t cda_entry;
171     uint32_t cda_addr0;
172     uint32_t cda_addr1;
173     uint32_t cda_addr2;
174     } __attribute__((__packed__));
175    
176     /*
177     * SONIC register file.
178     *
179     * NOTE: We define these as indices, and use a register map to deal
180     * with different address strides.
181     */
182    
183     #define SONIC_CR 0x00 /* Command Register */
184     #define CR_HTX (1U << 0) /* Halt Transmission */
185     #define CR_TXP (1U << 1) /* Transmit Packets */
186     #define CR_RXDIS (1U << 2) /* Receiver Disable */
187     #define CR_RXEN (1U << 3) /* Receiver Enable */
188     #define CR_STP (1U << 4) /* Stop Timer */
189     #define CR_ST (1U << 5) /* Start Timer */
190     #define CR_RST (1U << 7) /* Software Reset */
191     #define CR_RRRA (1U << 8) /* Read RRA */
192     #define CR_LCAM (1U << 9) /* Load CAM */
193    
194     #define SONIC_DCR 0x01 /* Data Configuration Register */
195     #define DCR_TFT0 (1U << 0) /* Transmit FIFO Threshold (lo) */
196     #define DCR_TFT1 (1U << 1) /* Transmit FIFO Threshold (hi) */
197     #define DCR_RFT0 (1U << 2) /* Receive FIFO Threshold (lo) */
198     #define DCR_RFT1 (1U << 3) /* Receive FIFO Threshold (hi) */
199     #define DCR_BMS (1U << 4) /* Block Mode Select for DMA */
200     #define DCR_DW (1U << 5) /* Data Width Select */
201     #define DCR_WC0 (1U << 6) /* Wait State Control (lo) */
202     #define DCR_WC1 (1U << 7) /* Wait State Control (hi) */
203     #define DCR_USR0 (1U << 8) /* User Definable Pin 0 */
204     #define DCR_USR1 (1U << 9) /* User Definable Pin 1 */
205     #define DCR_SBUS (1U << 10) /* Synchronous Bus Mode */
206     #define DCR_PO0 (1U << 11) /* Programmable Output 0 */
207     #define DCR_PO1 (1U << 12) /* Programmable Output 1 */
208     #define DCR_LBR (1U << 13) /* Latched Bus Retry */
209     #define DCR_EXBUS (1U << 15) /* Extended Bus Mode */
210    
211     #define SONIC_RCR 0x02 /* Receive Control Register */
212     #define RCR_PRX (1U << 0) /* Packet Received OK */
213     #define RCR_LBK (1U << 1) /* Loopback Packet Received */
214     #define RCR_FAER (1U << 2) /* Frame Alignment Error */
215     #define RCR_CRCR (1U << 3) /* CRC Error */
216     #define RCR_COL (1U << 4) /* Collision Activity */
217     #define RCR_CRS (1U << 5) /* Carrier Sense Activity */
218     #define RCR_LPKT (1U << 6) /* Last Packet in RBA */
219     #define RCR_BC (1U << 7) /* Broadcast Packet Received */
220     #define RCR_MC (1U << 8) /* Multicast Packet Received */
221     #define RCR_LB0 (1U << 9) /* Loopback Control 0 */
222     #define RCR_LB1 (1U << 10) /* Loopback Control 1 */
223     #define RCR_AMC (1U << 11) /* Accept All Multicast Packets */
224     #define RCR_PRO (1U << 12) /* Physical Promiscuous Packets */
225     #define RCR_BRD (1U << 13) /* Accept Broadcast Packets */
226     #define RCR_RNT (1U << 14) /* Accept Runt Packets */
227     #define RCR_ERR (1U << 15) /* Accept Packets with Errors */
228    
229     #define SONIC_TCR 0x03 /* Transmit Control Register */
230     #define TCR_PTX (1U << 0) /* Packet Transmitted OK */
231     #define TCR_BCM (1U << 1) /* Byte Count Mismatch */
232     #define TCR_FU (1U << 2) /* FIFO Underrun */
233     #define TCR_PMB (1U << 3) /* Packet Monitored Bad */
234     #define TCR_OWC (1U << 5) /* Out of Window Collision */
235     #define TCR_EXC (1U << 6) /* Excessive Collisions */
236     #define TCR_CRSL (1U << 7) /* Carrier Sense Lost */
237     #define TCR_NCRS (1U << 8) /* No Carrier Sense */
238     #define TCR_DEF (1U << 9) /* Deferred Transmission */
239     #define TCR_EXD (1U << 10) /* Excessive Deferral */
240     #define TCR_EXDIS (1U << 12) /* Disable Excessive Deferral Timer */
241     #define TCR_CRCI (1U << 13) /* CRC Inhibit */
242     #define TCR_POWC (1U << 14) /* Programmed Out of Window Col. Tmr */
243     #define TCR_PINT (1U << 15) /* Programmable Interrupt */
244    
245     #define SONIC_IMR 0x04 /* Interrupt Mask Register */
246     #define IMR_RFO (1U << 0) /* Rx FIFO Overrun */
247     #define IMR_MP (1U << 1) /* Missed Packet Tally */
248     #define IMR_FAE (1U << 2) /* Frame Alignment Error Tally */
249     #define IMR_CRC (1U << 3) /* CRC Tally */
250     #define IMR_RBA (1U << 4) /* RBA Exceeded */
251     #define IMR_RBE (1U << 5) /* Rx Buffers Exhausted */
252     #define IMR_RDE (1U << 6) /* Rx Descriptors Exhausted */
253     #define IMR_TC (1U << 7) /* Timer Complete */
254     #define IMR_TXER (1U << 8) /* Transmit Error */
255     #define IMR_PTX (1U << 9) /* Transmit OK */
256     #define IMR_PRX (1U << 10) /* Packet Received */
257     #define IMR_PINT (1U << 11) /* Programmable Interrupt */
258     #define IMR_LCD (1U << 12) /* Load CAM Done */
259     #define IMR_HBL (1U << 13) /* Heartbeat Lost */
260     #define IMR_BR (1U << 14) /* Bus Retry Occurred */
261    
262     #define SONIC_ISR 0x05 /* Interrupt Status Register */
263     /* See IMR bits. */
264    
265     #define SONIC_UTDAR 0x06 /* Upper Tx Descriptor Adress Register */
266    
267     #define SONIC_CTDAR 0x07 /* Current Tx Descriptor Address Register */
268    
269     #define SONIC_TPS 0x08 /* Transmit Packet Size */
270    
271     #define SONIC_TFC 0x09 /* Transmit Fragment Count */
272    
273     #define SONIC_TSA0 0x0a /* Transmit Start Address (lo) */
274    
275     #define SONIC_TSA1 0x0b /* Transmit Start Address (hi) */
276    
277     #define SONIC_TFS 0x0c /* Transmit Fragment Size */
278    
279     #define SONIC_URDAR 0x0d /* Upper Rx Descriptor Address Register */
280    
281     #define SONIC_CRDAR 0x0e /* Current Rx Descriptor Address Register */
282    
283     #define SONIC_CRBA0 0x0f /* Current Receive Buffer Address (lo) */
284    
285     #define SONIC_CRBA1 0x10 /* Current Receive Buffer Address (hi) */
286    
287     #define SONIC_RBWC0 0x11 /* Remaining Buffer Word Count 0 */
288    
289     #define SONIC_RBWC1 0x12 /* Remaining Buffer Word Count 1 */
290    
291     #define SONIC_EOBC 0x13 /* End Of Buffer Word Count */
292    
293     #define SONIC_URRAR 0x14 /* Upper Rx Resource Address Register */
294    
295     #define SONIC_RSAR 0x15 /* Resource Start Address Register */
296    
297     #define SONIC_REAR 0x16 /* Resource End Address Register */
298    
299     #define SONIC_RRR 0x17 /* Resource Read Register */
300    
301     #define SONIC_RWR 0x18 /* Resource Write Register */
302    
303     #define SONIC_TRBA0 0x19 /* Temporary Receive Buffer Address (lo) */
304    
305     #define SONIC_TRBA1 0x1a /* Temporary Receive Buffer Address (hi) */
306    
307     #define SONIC_TBWC0 0x1b /* Temporary Buffer Word Count 0 */
308    
309     #define SONIC_TBWC1 0x1c /* Temporary Buffer Word Count 1 */
310    
311     #define SONIC_ADDR0 0x1d /* Address Generator 0 */
312    
313     #define SONIC_ADDR1 0x1e /* Address Generator 1 */
314    
315     #define SONIC_LLFA 0x1f /* Last Link Field Address */
316    
317     #define SONIC_TTDA 0x20 /* Temporary Tx Descriptor Address */
318    
319     #define SONIC_CEP 0x21 /* CAM Entry Pointer */
320    
321     #define SONIC_CAP2 0x22 /* CAM Address Port 2 */
322    
323     #define SONIC_CAP1 0x23 /* CAM Address Port 1 */
324    
325     #define SONIC_CAP0 0x24 /* CAM Address Port 0 */
326    
327     #define SONIC_CER 0x25 /* CAM Enable Register */
328    
329     #define SONIC_CDP 0x26 /* CAM Descriptor Pointer */
330    
331     #define SONIC_CDC 0x27 /* CAM Descriptor Count */
332    
333     #define SONIC_SRR 0x28 /* Silicon Revision Register */
334    
335     #define SONIC_WT0 0x29 /* Watchdog Timer 0 */
336    
337     #define SONIC_WT1 0x2a /* Watchdog Timer 1 */
338    
339     #define SONIC_RSC 0x2b /* Receive Sequence Counter */
340    
341     #define SONIC_CRCETC 0x2c /* CRC Error Tally Count */
342    
343     #define SONIC_FAET 0x2d /* Frame Alignment Error Tally */
344    
345     #define SONIC_MPT 0x2e /* Missed Packet Tally */
346    
347     #define SONIC_DCR2 0x3f /* Data Configuration Register 2 */
348     #define DCR2_RJCM (1U << 0) /* Reject on CAM Match */
349     #define DCR2_PCNM (1U << 1) /* Packet Compress When not Matched */
350     #define DCR2_PCM (1U << 2) /* Packet Compress When Matched */
351     #define DCR2_PH (1U << 4) /* Program Hold */
352     #define DCR2_EXPO0 (1U << 12) /* Extended Programmable Output 0 */
353     #define DCR2_EXPO1 (1U << 13) /* Extended Programmable Output 1 */
354     #define DCR2_EXPO2 (1U << 14) /* Extended Programmable Output 2 */
355     #define DCR2_EXPO3 (1U << 15) /* Extended Programmable Output 3 */
356    
357     #define SONIC_NREGS 0x40
358    
359     #endif /* _DEV_IC_DP83932REG_H_ */
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