28 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
29 |
* |
* |
30 |
* |
* |
31 |
* $Id: devices.h,v 1.176 2005/08/05 09:11:49 debug Exp $ |
* $Id: devices.h,v 1.184 2005/10/03 01:07:48 debug Exp $ |
32 |
* |
* |
33 |
* Memory mapped devices. |
* Memory mapped devices. |
34 |
* |
* |
243 |
uint64_t baseaddr, int vfb_type, int visible_xsize, int visible_ysize, |
uint64_t baseaddr, int vfb_type, int visible_xsize, int visible_ysize, |
244 |
int xsize, int ysize, int bit_depth, char *name); |
int xsize, int ysize, int bit_depth, char *name); |
245 |
|
|
246 |
|
/* dev_footbridge: */ |
247 |
|
#define N_FOOTBRIDGE_TIMERS 4 |
248 |
|
struct footbridge_data { |
249 |
|
struct pci_data *pcibus; |
250 |
|
|
251 |
|
int console_handle; |
252 |
|
|
253 |
|
int timer_tick_countdown[N_FOOTBRIDGE_TIMERS]; |
254 |
|
uint32_t timer_load[N_FOOTBRIDGE_TIMERS]; |
255 |
|
uint32_t timer_value[N_FOOTBRIDGE_TIMERS]; |
256 |
|
uint32_t timer_control[N_FOOTBRIDGE_TIMERS]; |
257 |
|
|
258 |
|
uint32_t irq_status; |
259 |
|
uint32_t irq_enable; |
260 |
|
|
261 |
|
uint32_t fiq_status; |
262 |
|
uint32_t fiq_enable; |
263 |
|
}; |
264 |
|
|
265 |
/* dev_gt.c: */ |
/* dev_gt.c: */ |
266 |
#define DEV_GT_LENGTH 0x1000 |
#define DEV_GT_LENGTH 0x1000 |
267 |
int dev_gt_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, |
int dev_gt_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, |
618 |
struct vr41xx_data *dev_vr41xx_init(struct machine *machine, |
struct vr41xx_data *dev_vr41xx_init(struct machine *machine, |
619 |
struct memory *mem, int cpumodel); |
struct memory *mem, int cpumodel); |
620 |
|
|
|
/* dev_wdc.c: */ |
|
|
#define DEV_WDC_LENGTH 0x8 |
|
|
int dev_wdc_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *); |
|
|
void dev_wdc_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, int irq_nr, int base_drive); |
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|
|
|
621 |
/* dev_wdsc.c: */ |
/* dev_wdsc.c: */ |
622 |
#define DEV_WDSC_NREGS 0x100 /* 8-bit register select */ |
#define DEV_WDSC_NREGS 0x100 /* 8-bit register select */ |
623 |
#define DEV_WDSC_LENGTH 0x10 |
#define DEV_WDSC_LENGTH 0x10 |