/[gxemul]/trunk/src/include/devices.h
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Contents of /trunk/src/include/devices.h

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Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 26246 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 #ifndef DEVICES_H
2 #define DEVICES_H
3
4 /*
5 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: devices.h,v 1.212 2006/06/16 18:31:26 debug Exp $
32 *
33 * Memory mapped devices.
34 *
35 * TODO: Separate into lots of smaller files? That might speed up a compile,
36 * but I'm not sure that it's a price worth paying.
37 */
38
39 #include <sys/types.h>
40 #include <inttypes.h>
41
42 struct cpu;
43 struct machine;
44 struct memory;
45 struct pci_data;
46
47 /* #ifdef WITH_X11
48 #include <X11/Xlib.h>
49 #endif */
50
51 /* dev_8259.c: */
52 struct pic8259_data {
53 int irq_nr; /* if connected to another 8259 */
54
55 int irq_base;
56 int current_command;
57
58 int init_state;
59
60 int priority_reg;
61 uint8_t irr; /* interrupt request register */
62 uint8_t isr; /* interrupt in-service register */
63 uint8_t ier; /* interrupt enable register */
64 };
65
66 /* dev_dec_ioasic.c: */
67 #define DEV_DEC_IOASIC_LENGTH 0x80100
68 #define N_DEC_IOASIC_REGS (0x1f0 / 0x10)
69 #define MAX_IOASIC_DMA_FUNCTIONS 8
70 struct dec_ioasic_data {
71 uint32_t reg[N_DEC_IOASIC_REGS];
72 int (*(dma_func[MAX_IOASIC_DMA_FUNCTIONS]))(struct cpu *, void *, uint64_t addr, size_t dma_len, int tx);
73 void *dma_func_extra[MAX_IOASIC_DMA_FUNCTIONS];
74 int rackmount_flag;
75 };
76 int dev_dec_ioasic_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
77 struct dec_ioasic_data *dev_dec_ioasic_init(struct cpu *cpu, struct memory *mem, uint64_t baseaddr, int rackmount_flag);
78
79 /* dev_algor.c: */
80 struct algor_data {
81 uint64_t base_addr;
82 };
83
84 /* dev_asc.c: */
85 #define DEV_ASC_DEC_LENGTH 0x40000
86 #define DEV_ASC_PICA_LENGTH 0x1000
87 #define DEV_ASC_DEC 1
88 #define DEV_ASC_PICA 2
89 int dev_asc_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
90 void dev_asc_init(struct machine *machine, struct memory *mem, uint64_t baseaddr,
91 int irq_nr, void *turbochannel, int mode,
92 size_t (*dma_controller)(void *dma_controller_data,
93 unsigned char *data, size_t len, int writeflag),
94 void *dma_controller_data);
95
96 /* dev_au1x00.c: */
97 struct au1x00_ic_data {
98 int ic_nr;
99 uint32_t request0_int;
100 uint32_t request1_int;
101 uint32_t config0;
102 uint32_t config1;
103 uint32_t config2;
104 uint32_t source;
105 uint32_t assign_request;
106 uint32_t wakeup;
107 uint32_t mask;
108 };
109
110 int dev_au1x00_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
111 struct au1x00_ic_data *dev_au1x00_init(struct machine *machine, struct memory *mem);
112
113 /* dev_bebox.c: */
114 struct bebox_data {
115 /* The 5 motherboard registers: */
116 uint32_t cpu0_int_mask;
117 uint32_t cpu1_int_mask;
118 uint32_t int_status;
119 uint32_t xpi;
120 uint32_t resets;
121 };
122
123 /* dev_bt431.c: */
124 #define DEV_BT431_LENGTH 0x20
125 #define DEV_BT431_NREGS 0x800 /* ? */
126 int dev_bt431_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
127 struct vfb_data;
128 void dev_bt431_init(struct memory *mem, uint64_t baseaddr, struct vfb_data *vfb_data, int color_fb_flag);
129
130 /* dev_bt455.c: */
131 #define DEV_BT455_LENGTH 0x20
132 int dev_bt455_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
133 struct vfb_data;
134 void dev_bt455_init(struct memory *mem, uint64_t baseaddr, struct vfb_data *vfb_data);
135
136 /* dev_bt459.c: */
137 #define DEV_BT459_LENGTH 0x20
138 #define DEV_BT459_NREGS 0x1000
139 #define BT459_PX 1 /* px[g] */
140 #define BT459_BA 2 /* cfb */
141 #define BT459_BBA 3 /* sfb */
142 int dev_bt459_access(struct cpu *cpu, struct memory *mem,
143 uint64_t relative_addr, unsigned char *data, size_t len,
144 int writeflag, void *);
145 struct vfb_data;
146 void dev_bt459_init(struct machine *machine, struct memory *mem,
147 uint64_t baseaddr, uint64_t baseaddr_irq, struct vfb_data *vfb_data,
148 int color_fb_flag, int irq_nr, int type);
149
150 /* dev_cons.c: */
151 struct cons_data {
152 int console_handle;
153 int irq_nr;
154 int in_use;
155 };
156
157 /* dev_colorplanemask.c: */
158 #define DEV_COLORPLANEMASK_LENGTH 0x0000000000000010
159 int dev_colorplanemask_access(struct cpu *cpu, struct memory *mem,
160 uint64_t relative_addr, unsigned char *data, size_t len,
161 int writeflag, void *);
162 void dev_colorplanemask_init(struct memory *mem, uint64_t baseaddr,
163 unsigned char *color_plane_mask);
164
165 /* dev_cpc700.c: */
166 struct cpc700_data {
167 struct pci_data *pci_data;
168 uint32_t sr; /* Status register (interrupt) */
169 uint32_t er; /* Enable register */
170 };
171 struct cpc700_data *dev_cpc700_init(struct machine *, struct memory *);
172
173 /* dev_dc7085.c: */
174 #define DEV_DC7085_LENGTH 0x0000000000000080
175 /* see dc7085.h for more info */
176 void dev_dc7085_tick(struct cpu *cpu, void *);
177 int dev_dc7085_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
178 int dev_dc7085_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, int irq_nr, int use_fb);
179
180 /* dev_dec5800.c: */
181 #define DEV_DEC5800_LENGTH 0x1000 /* ? */
182 struct dec5800_data {
183 uint32_t csr;
184 uint32_t vector_0x50;
185 };
186 int dev_dec5800_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
187 struct dec5800_data *dev_dec5800_init(struct machine *machine, struct memory *mem, uint64_t baseaddr);
188 /* 16 slots, 0x2000 bytes each */
189 #define DEV_DECBI_LENGTH 0x20000
190 int dev_decbi_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
191 void dev_decbi_init(struct memory *mem, uint64_t baseaddr);
192 #define DEV_DECCCA_LENGTH 0x10000 /* ? */
193 #define DEC_DECCCA_BASEADDR 0x19000000 /* ? I just made this up */
194 int dev_deccca_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
195 void dev_deccca_init(struct memory *mem, uint64_t baseaddr);
196 #define DEV_DECXMI_LENGTH 0x800000
197 int dev_decxmi_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
198 void dev_decxmi_init(struct memory *mem, uint64_t baseaddr);
199
200 /* dev_eagle.c: */
201 struct pci_data *dev_eagle_init(struct machine *machine, struct memory *mem,
202 int irqbase, int pciirq);
203
204 /* dev_fb.c: */
205 #define DEV_FB_LENGTH 0x3c0000 /* 3c0000 to not colide with */
206 /* turbochannel rom, */
207 /* otherwise size = 4MB */
208 /* Type: */
209 #define VFB_GENERIC 0
210 #define VFB_HPC 1
211 #define VFB_DEC_VFB01 2
212 #define VFB_DEC_VFB02 3
213 #define VFB_DEC_MAXINE 4
214 #define VFB_PLAYSTATION2 5
215 /* Extra flags: */
216 #define VFB_REVERSE_START 0x10000
217 struct vfb_data {
218 int vfb_type;
219
220 int vfb_scaledown;
221
222 int xsize;
223 int ysize;
224 int bit_depth;
225 int color32k; /* hack for 16-bit HPCmips */
226 int psp_15bit; /* playstation portable hack */
227
228 unsigned char color_plane_mask;
229
230 int bytes_per_line; /* cached */
231
232 int visible_xsize;
233 int visible_ysize;
234
235 size_t framebuffer_size;
236 int x11_xsize, x11_ysize;
237
238 int update_x1, update_y1, update_x2, update_y2;
239
240 /* RGB palette for <= 8 bit modes: (r,g,b bytes for each) */
241 unsigned char rgb_palette[256 * 3];
242
243 void (*redraw_func)(struct vfb_data *, int, int);
244
245 /* These should always be in sync: */
246 unsigned char *framebuffer;
247 struct fb_window *fb_window;
248 };
249 #define VFB_MFB_BT455 0x100000
250 #define VFB_MFB_BT431 0x180000
251 #define VFB_MFB_VRAM 0x200000
252 #define VFB_CFB_BT459 0x200000
253 void set_grayscale_palette(struct vfb_data *d, int ncolors);
254 void dev_fb_resize(struct vfb_data *d, int new_xsize, int new_ysize);
255 void dev_fb_setcursor(struct vfb_data *d, int cursor_x, int cursor_y, int on,
256 int cursor_xsize, int cursor_ysize);
257 void framebuffer_blockcopyfill(struct vfb_data *d, int fillflag, int fill_r,
258 int fill_g, int fill_b, int x1, int y1, int x2, int y2,
259 int from_x, int from_y);
260 void dev_fb_tick(struct cpu *, void *);
261 int dev_fb_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
262 unsigned char *data, size_t len, int writeflag, void *);
263 struct vfb_data *dev_fb_init(struct machine *machine, struct memory *mem,
264 uint64_t baseaddr, int vfb_type, int visible_xsize, int visible_ysize,
265 int xsize, int ysize, int bit_depth, char *name);
266
267 /* dev_footbridge: */
268 #define N_FOOTBRIDGE_TIMERS 4
269 struct footbridge_data {
270 struct pci_data *pcibus;
271
272 int console_handle;
273
274 int timer_tick_countdown[N_FOOTBRIDGE_TIMERS];
275 uint32_t timer_load[N_FOOTBRIDGE_TIMERS];
276 uint32_t timer_value[N_FOOTBRIDGE_TIMERS];
277 uint32_t timer_control[N_FOOTBRIDGE_TIMERS];
278 int timer_being_read;
279 int timer_poll_mode;
280
281 uint32_t irq_status;
282 uint32_t irq_enable;
283
284 uint32_t fiq_status;
285 uint32_t fiq_enable;
286 };
287
288 /* dev_gc.c: */
289 struct gc_data {
290 int reassert_irq;
291 uint32_t status_hi;
292 uint32_t status_lo;
293 uint32_t enable_hi;
294 uint32_t enable_lo;
295 };
296 struct gc_data *dev_gc_init(struct machine *, struct memory *, uint64_t addr,
297 int reassert_irq);
298
299 /* dev_gt.c: */
300 #define DEV_GT_LENGTH 0x1000
301 int dev_gt_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
302 unsigned char *data, size_t len, int writeflag, void *);
303 struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
304 uint64_t baseaddr, int irq_nr, int pciirq, int type);
305
306 /* dev_i80321.c: */
307 struct i80321_data {
308 /* Interrupt Controller */
309 int reassert_irq;
310 uint32_t status;
311 uint32_t enable;
312
313 uint32_t pci_addr;
314 struct pci_data *pci_bus;
315
316 /* Memory Controller: */
317 uint32_t mcu_reg[0x100 / sizeof(uint32_t)];
318 };
319
320 /* dev_jazz.c: */
321 #define DEV_JAZZ_LENGTH 0x280
322 struct jazz_data {
323 struct cpu *cpu;
324
325 /* Jazz stuff: */
326 uint32_t int_enable_mask;
327 uint32_t int_asserted;
328
329 /* ISA stuff: */
330 uint32_t isa_int_enable_mask;
331 uint32_t isa_int_asserted;
332
333 int interval;
334 int interval_start;
335
336 int jazz_timer_value;
337 int jazz_timer_current;
338
339 uint64_t dma_translation_table_base;
340 uint64_t dma_translation_table_limit;
341
342 uint32_t dma0_mode;
343 uint32_t dma0_enable;
344 uint32_t dma0_count;
345 uint32_t dma0_addr;
346
347 uint32_t dma1_mode;
348 /* same for dma1,2,3 actually (TODO) */
349
350 int led;
351 };
352 size_t dev_jazz_dma_controller(void *dma_controller_data,
353 unsigned char *data, size_t len, int writeflag);
354
355 /* dev_kn01.c: */
356 #define DEV_KN01_CSR_LENGTH 0x0000000000000004
357 int dev_kn01_csr_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
358 void dev_kn01_csr_init(struct memory *mem, uint64_t baseaddr, int color_fb);
359 #define DEV_VDAC_LENGTH 0x20
360 #define DEV_VDAC_MAPWA 0x00
361 #define DEV_VDAC_MAP 0x04
362 #define DEV_VDAC_MASK 0x08
363 #define DEV_VDAC_MAPRA 0x0c
364 #define DEV_VDAC_OVERWA 0x10
365 #define DEV_VDAC_OVER 0x14
366 #define DEV_VDAC_OVERRA 0x1c
367 int dev_vdac_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
368 void dev_vdac_init(struct memory *mem, uint64_t baseaddr, unsigned char *rgb_palette, int color_fb_flag);
369
370 /* dev_kn02.c: */
371 struct kn02_csr {
372 uint8_t csr[sizeof(uint32_t)];
373 uint8_t filler[4096 - sizeof(uint32_t)]; /* for dyntrans mapping */
374 };
375 int dev_kn02_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
376 struct kn02_csr *dev_kn02_init(struct cpu *cpu, struct memory *mem,
377 uint64_t baseaddr);
378
379 /* dev_kn220.c: */
380 #define DEV_DEC5500_IOBOARD_LENGTH 0x100000
381 int dev_dec5500_ioboard_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
382 struct dec5500_ioboard_data *dev_dec5500_ioboard_init(struct cpu *cpu, struct memory *mem, uint64_t baseaddr);
383 #define DEV_SGEC_LENGTH 0x1000
384 int dev_sgec_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
385 void dev_sgec_init(struct memory *mem, uint64_t baseaddr, int irq_nr);
386
387 /* dev_kn230.c: */
388 struct kn230_csr {
389 uint32_t csr;
390 };
391
392 /* dev_le.c: */
393 #define DEV_LE_LENGTH 0x1c0200
394 int dev_le_access(struct cpu *cpu, struct memory *mem,
395 uint64_t relative_addr, unsigned char *data, size_t len,
396 int writeflag, void *);
397 void dev_le_init(struct machine *machine, struct memory *mem,
398 uint64_t baseaddr, uint64_t buf_start, uint64_t buf_end,
399 int irq_nr, int len);
400
401 /* dev_m700_fb.c: */
402 #define DEV_M700_FB_LENGTH 0x10000 /* TODO? */
403 int dev_m700_fb_access(struct cpu *cpu, struct memory *mem,
404 uint64_t relative_addr, unsigned char *data, size_t len,
405 int writeflag, void *);
406 void dev_m700_fb_init(struct machine *machine, struct memory *mem,
407 uint64_t baseaddr, uint64_t baseaddr2);
408
409 /* dev_malta.c: */
410 struct malta_data {
411 uint8_t assert_lo;
412 uint8_t assert_hi;
413 uint8_t disable_lo;
414 uint8_t disable_hi;
415 int poll_mode;
416 };
417
418 /* dev_mc146818.c: */
419 #define DEV_MC146818_LENGTH 0x0000000000000100
420 #define MC146818_DEC 0
421 #define MC146818_PC_CMOS 1
422 #define MC146818_ARC_NEC 2
423 #define MC146818_ARC_JAZZ 3
424 #define MC146818_SGI 4
425 #define MC146818_CATS 5
426 #define MC146818_ALGOR 6
427 #define MC146818_PMPPC 7
428 /* see mc146818reg.h for more info */
429 void dev_mc146818_tick(struct cpu *cpu, void *);
430 int dev_mc146818_access(struct cpu *cpu, struct memory *mem,
431 uint64_t relative_addr, unsigned char *data, size_t len,
432 int writeflag, void *);
433 void dev_mc146818_init(struct machine *machine, struct memory *mem,
434 uint64_t baseaddr, int irq_nr, int access_style, int addrdiv);
435
436 /* dev_pckbc.c: */
437 #define DEV_PCKBC_LENGTH 0x10
438 #define PCKBC_8042 0
439 #define PCKBC_8242 1
440 #define PCKBC_JAZZ 3
441 int dev_pckbc_access(struct cpu *cpu, struct memory *mem,
442 uint64_t relative_addr, unsigned char *data, size_t len,
443 int writeflag, void *);
444 int dev_pckbc_init(struct machine *machine, struct memory *mem,
445 uint64_t baseaddr, int type, int keyboard_irqnr, int mouse_irqnr,
446 int in_use, int pc_style_flag);
447
448 /* dev_pmppc.c: */
449 int dev_pmppc_board_access(struct cpu *cpu, struct memory *mem,
450 uint64_t relative_addr, unsigned char *data, size_t len, int writeflag,
451 void *);
452 void dev_pmppc_init(struct memory *mem);
453
454 /* dev_ps2_spd.c: */
455 #define DEV_PS2_SPD_LENGTH 0x800
456 int dev_ps2_spd_access(struct cpu *cpu, struct memory *mem,
457 uint64_t relative_addr, unsigned char *data, size_t len,
458 int writeflag, void *);
459 void dev_ps2_spd_init(struct machine *machine, struct memory *mem,
460 uint64_t baseaddr);
461
462 /* dev_ps2_stuff.c: */
463 #include "ps2_dmacreg.h"
464 #define N_PS2_DMA_CHANNELS 10
465 #define N_PS2_TIMERS 4
466 struct ps2_data {
467 uint32_t timer_count[N_PS2_TIMERS];
468 uint32_t timer_comp[N_PS2_TIMERS];
469 uint32_t timer_mode[N_PS2_TIMERS];
470 uint32_t timer_hold[N_PS2_TIMERS]; /* NOTE: only 0 and 1 are valid */
471
472 uint64_t dmac_reg[DMAC_REGSIZE / 0x10];
473
474 uint64_t other_memory_base[N_PS2_DMA_CHANNELS];
475
476 uint32_t intr;
477 uint32_t imask;
478 uint32_t sbus_smflg;
479 };
480 #define DEV_PS2_STUFF_LENGTH 0x10000
481 int dev_ps2_stuff_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
482 struct ps2_data *dev_ps2_stuff_init(struct machine *machine, struct memory *mem, uint64_t baseaddr);
483
484 /* dev_pmagja.c: */
485 #define DEV_PMAGJA_LENGTH 0x3c0000
486 int dev_pmagja_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
487 void dev_pmagja_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, int irq_nr);
488
489 /* dev_prep.c: */
490 struct prep_data {
491 uint32_t int_status;
492 };
493
494 /* dev_px.c: */
495 struct px_data {
496 struct memory *fb_mem;
497 struct vfb_data *vfb_data;
498 int type;
499 char *px_name;
500 int irq_nr;
501 int bitdepth;
502 int xconfig;
503 int yconfig;
504
505 uint32_t intr;
506 unsigned char sram[128 * 1024];
507 };
508 /* TODO: perhaps these types are wrong? */
509 #define DEV_PX_TYPE_PX 0
510 #define DEV_PX_TYPE_PXG 1
511 #define DEV_PX_TYPE_PXGPLUS 2
512 #define DEV_PX_TYPE_PXGPLUSTURBO 3
513 #define DEV_PX_LENGTH 0x3c0000
514 int dev_px_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
515 unsigned char *data, size_t len, int writeflag, void *);
516 void dev_px_init(struct machine *machine, struct memory *mem, uint64_t baseaddr,
517 int px_type, int irq_nr);
518
519 /* dev_ram.c: */
520 #define DEV_RAM_RAM 0
521 #define DEV_RAM_MIRROR 1
522 #define DEV_RAM_MIGHT_POINT_TO_DEVICES 0x10
523 int dev_ram_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
524 unsigned char *data, size_t len, int writeflag, void *);
525 void dev_ram_init(struct machine *machine, uint64_t baseaddr, uint64_t length,
526 int mode, uint64_t otheraddr);
527
528 /* dev_scc.c: */
529 #define DEV_SCC_LENGTH 0x1000
530 int dev_scc_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
531 unsigned char *data, size_t len, int writeflag, void *);
532 int dev_scc_dma_func(struct cpu *cpu, void *extra, uint64_t addr,
533 size_t dma_len, int tx);
534 void *dev_scc_init(struct machine *machine, struct memory *mem,
535 uint64_t baseaddr, int irq_nr, int use_fb, int scc_nr, int addrmul);
536
537 /* dev_sfb.c: */
538 #define DEV_SFB_LENGTH 0x400000
539 int dev_sfb_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
540 unsigned char *data, size_t len, int writeflag, void *);
541 void dev_sfb_init(struct machine *machine, struct memory *mem,
542 uint64_t baseaddr, struct vfb_data *vfb_data);
543
544 /* dev_sgi_gbe.c: */
545 #define DEV_SGI_GBE_LENGTH 0x1000000
546 int dev_sgi_gbe_access(struct cpu *cpu, struct memory *mem,
547 uint64_t relative_addr, unsigned char *data, size_t len, int writeflag,
548 void *);
549 void dev_sgi_gbe_init(struct machine *machine, struct memory *mem,
550 uint64_t baseaddr);
551
552 /* dev_sgi_ip20.c: */
553 #define DEV_SGI_IP20_LENGTH 0x40
554 #define DEV_SGI_IP20_BASE 0x1fb801c0
555 struct sgi_ip20_data {
556 int dummy;
557 };
558 int dev_sgi_ip20_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
559 struct sgi_ip20_data *dev_sgi_ip20_init(struct cpu *cpu, struct memory *mem, uint64_t baseaddr);
560
561 /* dev_sgi_ip22.c: */
562 #define DEV_SGI_IP22_LENGTH 0x100
563 #define DEV_SGI_IP22_IMC_LENGTH 0x100
564 #define DEV_SGI_IP22_UNKNOWN2_LENGTH 0x100
565 #define IP22_IMC_BASE 0x1fa00000
566 #define IP22_UNKNOWN2_BASE 0x1fb94000
567 struct sgi_ip22_data {
568 int guiness_flag;
569 uint32_t reg[DEV_SGI_IP22_LENGTH / 4];
570 uint32_t imc_reg[DEV_SGI_IP22_IMC_LENGTH / 4];
571 uint32_t unknown2_reg[DEV_SGI_IP22_UNKNOWN2_LENGTH / 4];
572 uint32_t unknown_timer;
573 };
574 int dev_sgi_ip22_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
575 struct sgi_ip22_data *dev_sgi_ip22_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, int guiness_flag);
576
577 /* dev_sgi_ip30.c: */
578 #define DEV_SGI_IP30_LENGTH 0x80000
579 struct sgi_ip30_data {
580 /* ip30: */
581 uint64_t imask0; /* 0x10000 */
582 uint64_t reg_0x10018;
583 uint64_t isr; /* 0x10030 */
584 uint64_t reg_0x20000;
585 uint64_t reg_0x30000;
586
587 /* ip30_2: */
588 uint64_t reg_0x0029c;
589
590 /* ip30_3: */
591 uint64_t reg_0x00284;
592
593 /* ip30_4: */
594 uint64_t reg_0x000b0;
595
596 /* ip30_5: */
597 uint64_t reg_0x00000;
598 };
599 int dev_sgi_ip30_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
600 struct sgi_ip30_data *dev_sgi_ip30_init(struct machine *machine, struct memory *mem, uint64_t baseaddr);
601
602 /* dev_sgi_ip32.c: */
603 #define DEV_CRIME_LENGTH 0x0000000000001000
604 struct crime_data {
605 unsigned char reg[DEV_CRIME_LENGTH];
606 int irq_nr;
607 int use_fb;
608 };
609 int dev_crime_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
610 struct crime_data *dev_crime_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, int irq_nr, int use_fb);
611 #define DEV_MACE_LENGTH 0x100
612 struct mace_data {
613 unsigned char reg[DEV_MACE_LENGTH];
614 int irqnr;
615 };
616 int dev_mace_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
617 struct mace_data *dev_mace_init(struct memory *mem, uint64_t baseaddr, int irqnr);
618 #define DEV_MACEPCI_LENGTH 0x1000
619 int dev_macepci_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
620 struct pci_data *dev_macepci_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, int pciirq);
621 #define DEV_SGI_MEC_LENGTH 0x1000
622 int dev_sgi_mec_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
623 void dev_sgi_mec_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, int irq_nr, unsigned char *macaddr);
624 #define DEV_SGI_UST_LENGTH 0x10000
625 int dev_sgi_ust_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
626 void dev_sgi_ust_init(struct memory *mem, uint64_t baseaddr);
627 #define DEV_SGI_MTE_LENGTH 0x10000
628 int dev_sgi_mte_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
629 void dev_sgi_mte_init(struct memory *mem, uint64_t baseaddr);
630
631 /* dev_sii.c: */
632 #define DEV_SII_LENGTH 0x100
633 void dev_sii_tick(struct cpu *cpu, void *);
634 int dev_sii_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
635 void dev_sii_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, uint64_t buf_start, uint64_t buf_end, int irq_nr);
636
637 /* dev_ssc.c: */
638 #define DEV_SSC_LENGTH 0x1000
639 int dev_ssc_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
640 void dev_ssc_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, int irq_nr, int use_fb, uint32_t *);
641
642 /* dev_turbochannel.c: */
643 #define DEV_TURBOCHANNEL_LEN 0x0470
644 int dev_turbochannel_access(struct cpu *cpu, struct memory *mem,
645 uint64_t relative_addr, unsigned char *data, size_t len,
646 int writeflag, void *);
647 void dev_turbochannel_init(struct machine *machine, struct memory *mem,
648 int slot_nr, uint64_t baseaddr, uint64_t endaddr, char *device_name,
649 int irq);
650
651 /* dev_uninorth.c: */
652 struct pci_data *dev_uninorth_init(struct machine *machine, struct memory *mem,
653 uint64_t addr, int irqbase, int pciirq);
654
655 /* dev_v3.c: */
656 struct v3_data {
657 struct pci_data *pci_data;
658 uint16_t lb_map0;
659 };
660 struct v3_data *dev_v3_init(struct machine *, struct memory *);
661
662 /* dev_vga.c: */
663 int dev_vga_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
664 unsigned char *data, size_t len, int writeflag, void *);
665 void dev_vga_init(struct machine *machine, struct memory *mem,
666 uint64_t videomem_base, uint64_t control_base, char *name);
667
668 /* dev_vr41xx.c: */
669 #define DEV_VR41XX_LENGTH 0x800 /* TODO? */
670 struct vr41xx_data {
671 int cpumodel;
672
673 int kiu_console_handle;
674 uint32_t kiu_offset;
675 int kiu_irq_nr;
676 int kiu_int_assert;
677 int d0;
678 int d1;
679 int d2;
680 int d3;
681 int d4;
682 int d5;
683 int dont_clear_next;
684 int escape_state;
685
686 /* See icureg.h in NetBSD for more info. */
687 uint16_t sysint1;
688 uint16_t msysint1;
689 uint16_t giuint;
690 uint16_t giumask;
691 uint16_t sysint2;
692 uint16_t msysint2;
693 };
694
695 int dev_vr41xx_access(struct cpu *cpu, struct memory *mem,
696 uint64_t relative_addr, unsigned char *data, size_t len,
697 int writeflag, void *);
698 struct vr41xx_data *dev_vr41xx_init(struct machine *machine,
699 struct memory *mem, int cpumodel);
700
701 /* dev_wdsc.c: */
702 #define DEV_WDSC_NREGS 0x100 /* 8-bit register select */
703 #define DEV_WDSC_LENGTH 0x10
704 int dev_wdsc_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *);
705 void dev_wdsc_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, int controller_nr, int irq_nr);
706
707 /* lk201.c: */
708 struct lk201_data {
709 int use_fb;
710 int console_handle;
711
712 void (*add_to_rx_queue)(void *,int,int);
713 void *add_data;
714
715 unsigned char keyb_buf[8];
716 int keyb_buf_pos;
717
718 int mouse_mode;
719 int mouse_revision; /* 0..15 */
720 int mouse_x, mouse_y, mouse_buttons;
721
722 int old_host_mouse_x;
723 int old_host_mouse_y;
724 int old_host_mouse_stays_put;
725 int mouse_check_interval;
726 int mouse_check_interval_reset;
727 };
728 void lk201_tick(struct lk201_data *);
729 void lk201_tx_data(struct lk201_data *, int port, int idata);
730 void lk201_init(struct lk201_data *d, int use_fb,
731 void (*add_to_rx_queue)(void *,int,int), int console_handle, void *);
732
733
734 #endif /* DEVICES_H */
735

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