/[gxemul]/trunk/src/include/dec_kn03.h
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Contents of /trunk/src/include/dec_kn03.h

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Revision 4 - (show annotations)
Mon Oct 8 16:18:00 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 9454 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============
1 /* gxemul: $Id: dec_kn03.h,v 1.3 2005/03/05 12:34:02 debug Exp $ */
2 /* The IOASIC stuff below seems to be using 0x40000 per slot */
3
4 /* $NetBSD: kn03.h,v 1.10 2000/02/29 04:41:57 nisimura Exp $ */
5
6 /*-
7 * Copyright (c) 1992, 1993
8 * The Regents of the University of California. All rights reserved.
9 *
10 * This code is derived from software contributed to Berkeley by
11 * The Mach Operating System project at Carnegie-Mellon University,
12 * Ralph Campbell and Rick Macklem.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. All advertising materials mentioning features or use of this software
23 * must display the following acknowledgement:
24 * This product includes software developed by the University of
25 * California, Berkeley and its contributors.
26 * 4. Neither the name of the University nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * SUCH DAMAGE.
41 *
42 * @(#)kn03.h 8.1 (Berkeley) 6/10/93
43 */
44
45 /*
46 * Mach Operating System
47 * Copyright (c) 1991,1990,1989 Carnegie Mellon University
48 * All Rights Reserved.
49 *
50 * Permission to use, copy, modify and distribute this software and
51 * its documentation is hereby granted, provided that both the copyright
52 * notice and this permission notice appear in all copies of the
53 * software, derivative works or modified versions, and any portions
54 * thereof, and that both notices appear in supporting documentation.
55 *
56 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
57 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
58 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
59 *
60 * Carnegie Mellon requests users of this software to return to
61 *
62 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
63 * School of Computer Science
64 * Carnegie Mellon University
65 * Pittsburgh PA 15213-3890
66 *
67 * any improvements or extensions that they make and grant Carnegie the
68 * rights to redistribute these changes.
69 */
70 /*
71 * Definitions specific to the KN03GA processors and 3MAX+
72 * DECstation 5000/240 mother board.
73 */
74
75 #ifndef MIPS_KN03_H
76 #define MIPS_KN03_H 1
77
78 /*
79 * 3MAX+'s Physical address space
80 */
81 #define KN03_PHYS_MIN 0x00000000 /* 512 Meg */
82 #define KN03_PHYS_MAX 0x1fffffff
83
84 /*
85 * Memory map
86 */
87 #define KN03_PHYS_MEMORY_START 0x00000000
88 #define KN03_PHYS_MEMORY_END 0x1dffffff /* 480 Meg */
89
90 /*
91 * I/O map
92 */
93 #define KN03_PHYS_TC_0_START 0x1e000000 /* TURBOchannel, slot 0 */
94 #define KN03_PHYS_TC_0_END 0x1e7fffff /* 8 Meg, option0 */
95
96 #define KN03_PHYS_TC_1_START 0x1e800000 /* TURBOchannel, slot 1 */
97 #define KN03_PHYS_TC_1_END 0x1effffff /* 8 Meg, option1 */
98
99 #define KN03_PHYS_TC_2_START 0x1f000000 /* TURBOchannel, slot 2 */
100 #define KN03_PHYS_TC_2_END 0x1f7fffff /* 8 Meg, option2 */
101
102 #define KN03_PHYS_TC_3_START 0x1f800000 /* TURBOchannel, slot 3 */
103 #define KN03_PHYS_TC_3_END 0x1fffffff /* 8 Meg, system devices */
104
105 #define KN03_PHYS_TC_START KN03_PHYS_TC_0_START
106 #define KN03_PHYS_TC_END KN03_PHYS_TC_3_END
107
108 #define KN03_TC_NSLOTS 4
109 #define KN03_TC_MIN 0
110 #define KN03_TC_MAX 2 /* don't look at system slot */
111
112 /*
113 * System module space (IOASIC)
114 */
115 #define KN03_SYS_ASIC ( KN03_PHYS_TC_3_START + 0x0000000 )
116 #define KN03_SYS_ROM_START ( KN03_SYS_ASIC + IOASIC_SLOT_0_START )
117 #define KN03_SYS_ASIC_REGS ( KN03_SYS_ASIC + IOASIC_SLOT_1_START )
118 #define KN03_SYS_ETHER_ADDRESS ( KN03_SYS_ASIC + IOASIC_SLOT_2_START )
119 #define KN03_SYS_LANCE ( KN03_SYS_ASIC + IOASIC_SLOT_3_START )
120 #define KN03_SYS_SCC_0 ( KN03_SYS_ASIC + IOASIC_SLOT_4_START )
121 #define KN03_SYS_SCC_1 ( KN03_SYS_ASIC + IOASIC_SLOT_6_START )
122 #define KN03_SYS_CLOCK ( KN03_SYS_ASIC + IOASIC_SLOT_8_START )
123 #define KN03_SYS_ERRADR ( KN03_SYS_ASIC + IOASIC_SLOT_9_START )
124 #define KN03_SYS_ERRSYN ( KN03_SYS_ASIC + IOASIC_SLOT_10_START )
125 #define KN03_SYS_CSR ( KN03_SYS_ASIC + IOASIC_SLOT_11_START )
126 #define KN03_SYS_SCSI ( KN03_SYS_ASIC + IOASIC_SLOT_12_START )
127 #define KN03_SYS_SCSI_DMA ( KN03_SYS_ASIC + IOASIC_SLOT_14_START )
128 #define KN03_SYS_BOOT_ROM_START ( KN03_PHYS_TC_3_START + 0x400000 )
129 #define KN03_SYS_BOOT_ROM_END ( KN03_PHYS_TC_3_START + 0x43ffff )
130
131 /*
132 * Interrupts
133 */
134 #define KN03_INT_FPA IP_LEV7 /* Floating Point coproc */
135 #define KN03_INT_HALTB IP_LEV6 /* Halt button */
136 #define KN03_INT_MEM IP_LEV5 /* Memory Errors */
137 #define KN03_INT_RTC IP_LEV3 /* RTC clock */
138 #define KN03_INT_ASIC IP_LEV2 /* All turbochannel */
139
140 #define KN03_REG_SCSI_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCSI_DMAPTR )
141 #define KN03_REG_SCSI_DMANPTR ( KN03_SYS_ASIC + IOASIC_SCSI_NEXTPTR )
142 #define KN03_REG_LANCE_DMAPTR ( KN03_SYS_ASIC + IOASIC_LANCE_DMAPTR )
143 #define KN03_REG_SCC_T1_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_T1_DMAPTR )
144 #define KN03_REG_SCC_R1_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_R1_DMAPTR )
145 #define KN03_REG_SCC_T2_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_T2_DMAPTR )
146 #define KN03_REG_SCC_R2_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_R2_DMAPTR )
147 #define KN03_REG_CSR ( KN03_SYS_ASIC + IOASIC_CSR )
148 #define KN03_REG_INTR ( KN03_SYS_ASIC + IOASIC_INTR )
149 #define KN03_REG_IMSK ( KN03_SYS_ASIC + IOASIC_IMSK )
150 #define KN03_REG_CURADDR ( KN03_SYS_ASIC + IOASIC_CURADDR )
151
152 #define KN03_REG_LANCE_DECODE ( KN03_SYS_ASIC + IOASIC_LANCE_DECODE )
153 #define KN03_REG_SCSI_DECODE ( KN03_SYS_ASIC + IOASIC_SCSI_DECODE )
154 #define KN03_REG_SCC0_DECODE ( KN03_SYS_ASIC + IOASIC_SCC0_DECODE )
155 #define KN03_REG_SCC1_DECODE ( KN03_SYS_ASIC + IOASIC_SCC1_DECODE )
156 # define KN03_LANCE_CONFIG 3
157 # define KN03_SCSI_CONFIG 14
158 # define KN03_SCC0_CONFIG (0x10|4)
159 # define KN03_SCC1_CONFIG (0x10|6)
160
161 #define KN03_REG_SCSI_SCR ( KN03_SYS_ASIC + IOASIC_SCSI_SCR )
162 #define KN03_REG_SCSI_SDR0 ( KN03_SYS_ASIC + IOASIC_SCSI_SDR0 )
163 #define KN03_REG_SCSI_SDR1 ( KN03_SYS_ASIC + IOASIC_SCSI_SDR1 )
164
165 /* NOTES
166
167 Memory access priority is, from higher to lower:
168 - DRAM refresh
169 - IO DMA (IO Control ASIC)
170 - Slot 2 DMA
171 - Slot 1 DMA
172 - Slot 0 DMA
173 - Processor
174
175 */
176
177 /*
178 * More system registers defines (IO Control ASIC)
179 */
180 /* (re)defines for the system Status and Control register (SSR) */
181 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */
182 #define KN03_CSR_LEDS 0x000000ff /* rw */
183 #define KN03_CSR_BNK32M 0x00000400 /* rw Memory bank stride */
184 #define KN03_CSR_CORRECT 0x00002000 /* rw ECC corrects single bit */
185 #define KN03_CSR_ECCMD 0x0000c000 /* rw ECC logic mode */
186
187 /* (re)defines for the System Interrupt and Mask Registers */
188 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */
189 #define KN03_INTR_PBNO 0x00000001 /* ro */
190 #define KN03_INTR_PBNC 0x00000002 /* ro */
191 #define KN03_INTR_SCSI_FIFO 0x00000004 /* ro */
192 #define KN03_INTR_PSWARN 0x00000010 /* ro */
193 #define KN03_INTR_CLOCK 0x00000020 /* ro */
194 #define KN03_INTR_SCC_0 0x00000040 /* ro */
195 #define KN03_INTR_SCC_1 0x00000080 /* ro */
196 #define KN03_INTR_LANCE 0x00000100 /* ro */
197 #define KN03_INTR_SCSI 0x00000200 /* ro */
198 #define KN03_INTR_NRMOD_JUMPER 0x00000400 /* ro */
199 #define KN03_INTR_TC_0 0x00000800 /* ro */
200 #define KN03_INTR_TC_1 0x00001000 /* ro */
201 #define KN03_INTR_TC_2 0x00002000 /* ro */
202 #define KN03_INTR_NVR_JUMPER 0x00004000 /* ro */
203 #define KN03_INTR_PROD_JUMPER 0x00008000 /* ro */
204
205 #define KN03_INTR_ASIC 0xff0f0004
206 #define KN03_IM0 0xff0f3bf0 /* all good ones enabled */
207
208 /*
209 * Error Address Register Bit Definitions
210 */
211 #define KN03_ERR_ADDRESS 0x07ffffff /* phys address */
212 #define KN03_ERR_RESERVED 0x08000000 /* unused */
213 #define KN03_ERR_ECCERR 0x10000000 /* ECC error */
214 #define KN03_ERR_WRITE 0x20000000 /* read/write transaction */
215 #define KN03_ERR_CPU 0x40000000 /* CPU or device initiator */
216 #define KN03_ERR_VALID 0x80000000 /* Info is valid */
217
218 /* ECC check/syndrome status register */
219 #define KN03_ECC_SYNLO 0x0000007f /* syndrome, even bank */
220 #define KN03_ECC_SNGLO 0x00000080 /* single bit err, " */
221 #define KN03_ECC_CHKLO 0x00007f00 /* check bits, " " */
222 #define KN03_ECC_VLDLO 0x00008000 /* info valid for " */
223 #define KN03_ECC_SYNHI 0x007f0000 /* syndrome, odd bank */
224 #define KN03_ECC_SNGHI 0x00800000 /* single bit err, " */
225 #define KN03_ECC_CHKHI 0x7f000000 /* check bits, " " */
226 #define KN03_ECC_VLDHI 0x80000000 /* info valid for " */
227
228 #endif /* MIPS_KN03_H */
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