/[gxemul]/trunk/src/include/dc21285reg.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/include/dc21285reg.h

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Revision 14 - (show annotations)
Mon Oct 8 16:18:51 2007 UTC (12 years ago) by dpavlin
File MIME type: text/plain
File size: 11495 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.

1 /* GXemul: $Id: dc21285reg.h,v 1.1 2005/09/13 20:56:54 debug Exp $ */
2 /* $NetBSD: dc21285reg.h,v 1.4 2003/01/17 22:29:43 thorpej Exp $ */
3
4 #ifndef DC21285REG_H
5 #define DC21285REG_H
6
7 /*
8 * Copyright (c) 1997,1998 Mark Brinicombe.
9 * Copyright (c) 1997,1998 Causality Limited
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by Mark Brinicombe
23 * for the NetBSD Project.
24 * 4. The name of the company nor the name of the author may be used to
25 * endorse or promote products derived from this software without specific
26 * prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
31 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
32 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
33 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 */
40
41 /*
42 * DC21285 register definitions
43 */
44
45 /* PCI registers in CSR space */
46
47 #define VENDOR_ID 0x00
48 #define DC21285_VENDOR_ID 0x1011
49 #define DEVICE_ID 0x02
50 #define DC21285_DEVICE_ID 0x1065
51 #define REVISION 0x08
52 #define CLASS 0x0A
53
54 /* Other PCI control / status registers */
55
56 #define OUTBOUND_INT_STATUS 0x030
57 #define OUTBOUND_INT_MASK 0x034
58 #define I2O_INBOUND_FIFO 0x040
59 #define I2O_OUTBOUND_FIFO 0x044
60
61 /* Mailbox registers */
62
63 #define MAILBOX_0 0x050
64 #define MAILBOX_1 0x054
65 #define MAILBOX_2 0x058
66 #define MAILBOX_3 0x05C
67
68 #define DOORBELL 0x060
69 #define DOORBELL_SETUP 0x064
70 #define ROM_WRITE_BYTE_ADDRESS 0x068
71
72 /* DMA Channel registers */
73
74 #define DMA_CHAN_1_BYTE_COUNT 0x80
75 #define DMA_CHAN_1_PCI_ADDR 0x84
76 #define DMA_CHAN_1_SDRAM_ADDR 0x88
77 #define DMA_CHAN_1_DESCRIPT 0x8C
78 #define DMA_CHAN_1_CONTROL 0x90
79 #define DMA_CHAN_2_BYTE_COUNT 0xA0
80 #define DMA_CHAN_2_PCI_ADDR 0xA4
81 #define DMA_CHAN_2_SDRAM_ADDR 0xA8
82 #define DMA_CHAN_2_DESCRIPTOR 0xAC
83 #define DMA_CHAN_2_CONTROL 0xB0
84
85 /* Offsets into DMA descriptor */
86
87 #define DMA_BYTE_COUNT 0
88 #define DMA_PCI_ADDRESS 4
89 #define DMA_SDRAM_ADDRESS 8
90 #define DMA_NEXT_DESCRIPTOR 12
91
92 /* DMA byte count register bits */
93
94 #define DMA_INTERBURST_SHIFT 24
95 #define DMA_PCI_TO_SDRAM 0
96 #define DMA_SDRAM_TO_PCI (1 << 30)
97 #define DMA_END_CHAIN (1 << 31)
98
99 /* DMA control bits */
100
101 #define DMA_ENABLE (1 << 0)
102 #define DMA_TRANSFER_DONE (1 << 2)
103 #define DMA_ERROR (1 << 3)
104 #define DMA_REGISTOR_DESCRIPTOR (1 << 4)
105 #define DMA_PCI_MEM_READ (0 << 5)
106 #define DMA_PCI_MEM_READ_LINE (1 << 5)
107 #define DMA_PCI_MEM_READ_MULTI1 (2 << 5)
108 #define DMA_PCI_MEM_READ_MULTI2 (3 << 5)
109 #define DMA_CHAIN_DONE (1 << 7)
110 #define DMA_INTERBURST_4 (0 << 8)
111 #define DMA_INTERBURST_8 (1 << 8)
112 #define DMA_INTERBURST_16 (2 << 8)
113 #define DMA_INTERBURST_32 (3 << 8)
114 #define DMA_PCI_LENGTH_8 0
115 #define DMA_PCI_LENGTH_16 (1 << 15)
116 #define DMA_SDRAM_LENGTH_1 (0 << 16)
117 #define DMA_SDRAM_LENGTH_2 (1 << 16)
118 #define DMA_SDRAM_LENGTH_4 (2 << 16)
119 #define DMA_SDRAM_LENGTH_8 (3 << 16)
120 #define DMA_SDRAM_LENGTH_16 (4 << 16)
121
122 /* CSR Base Address Mask */
123
124 #define CSR_BA_MASK 0x0F8
125 #define CSR_MASK_128B 0x00000000
126 #define CSR_MASK_512KB 0x00040000
127 #define CSR_MASK_1MB 0x000C0000
128 #define CSR_MASK_2MB 0x001C0000
129 #define CSR_MASK_4MB 0x003C0000
130 #define CSR_MASK_8MB 0x007C0000
131 #define CSR_MASK_16MB 0x00FC0000
132 #define CSR_MASK_32MB 0x01FC0000
133 #define CSR_MASK_64MB 0x03FC0000
134 #define CSR_MASK_128MB 0x07FC0000
135 #define CSR_MASK_256MB 0x0FFC0000
136 #define CSR_BA_OFFSET 0x0FC
137
138 /* SDRAM Base Address Mask */
139
140 #define SDRAM_BA_MASK 0x100
141 #define SDRAM_MASK_256KB 0x00000000
142 #define SDRAM_MASK_512KB 0x00040000
143 #define SDRAM_MASK_1MB 0x000C0000
144 #define SDRAM_MASK_2MB 0x001C0000
145 #define SDRAM_MASK_4MB 0x003C0000
146 #define SDRAM_MASK_8MB 0x007C0000
147 #define SDRAM_MASK_16MB 0x00FC0000
148 #define SDRAM_MASK_32MB 0x01FC0000
149 #define SDRAM_MASK_64MB 0x03FC0000
150 #define SDRAM_MASK_128MB 0x07FC0000
151 #define SDRAM_MASK_256MB 0x0FFC0000
152 #define SDRAM_WINDOW_DISABLE (1 << 31)
153 #define SDRAM_BA_OFFSET 0x104
154
155 /* Expansion ROM Base Address Mask */
156
157 #define EXPANSION_ROM_BA_MASK 0x108
158 #define ROM_MASK_1MB 0x00000000
159 #define ROM_MASK_2MB 0x00100000
160 #define ROM_MASK_4MB 0x00300000
161 #define ROM_MASK_8MB 0x00700000
162 #define ROM_MASK_16MB 0x00F00000
163 #define ROM_WINDOW_DISABLE (1 << 31)
164
165 /* SDRAM configuration */
166
167 #define SDRAM_TIMING 0x10C
168 #define SDRAM_ARRAY_SIZE_0 0x0
169 #define SDRAM_ARRAY_SIZE_1MB 0x1
170 #define SDRAM_ARRAY_SIZE_2MB 0x2
171 #define SDRAM_ARRAY_SIZE_4MB 0x3
172 #define SDRAM_ARRAY_SIZE_8MB 0x4
173 #define SDRAM_ARRAY_SIZE_16MB 0x5
174 #define SDRAM_ARRAY_SIZE_32MB 0x6
175 #define SDRAM_ARRAY_SIZE_64MB 0x7
176 #define SDRAM_2_BANKS 0
177 #define SDRAM_4_BANKS (1 << 3)
178 #define SDRAM_ADDRESS_MUX_SHIFT 4
179 #define SDRAM_ARRAY_BASE_SHIFT 20
180 #define SDRAM_ADDRESS_SIZE_0 0x110
181 #define SDRAM_ADDRESS_SIZE_1 0x114
182 #define SDRAM_ADDRESS_SIZE_2 0x118
183 #define SDRAM_ADDRESS_SIZE_3 0x11C
184
185 /* I2O registers */
186
187 #define I2O_INBOUND_FREE_HEAD 0x120
188 #define I2O_INBOUND_POST_TAIL 0x124
189 #define I2O_OUTBOUND_POST_HEAD 0x128
190 #define I2O_OUTBOUND_FREE_TAIL 0x12c
191 #define I2O_INBOUND_FREE_COUNT 0x130
192 #define I2O_OUTBOUND_POST_COUNT 0x134
193 #define I2O_INBOUND_POST_COUNT 0x138
194
195 /* Control register */
196
197 #define SA_CONTROL 0x13C
198 #define INITIALIZE_COMPLETE (1 << 0)
199 #define ASSERT_SERR (1 << 1)
200 #define RECEIVED_SERR (1 << 3)
201 #define SA_SDRAM_PARITY_ERROR (1 << 4)
202 #define PCI_SDRAM_PARITY_ERROR (1 << 5)
203 #define DMA_SDRAM_PARITY_ERROR (1 << 6)
204 #define DISCARD_TIMER_EXPIRED (1 << 8)
205 #define PCI_NOT_RESET (1 << 9)
206 #define WATCHDOG_ENABLE (1 << 13)
207 #define I2O_SIZE_256 (0 << 10)
208 #define I2O_SIZE_512 (1 << 10)
209 #define I2O_SIZE_1024 (2 << 10)
210 #define I2O_SIZE_2048 (3 << 10)
211 #define I2O_SIZE_4096 (4 << 10)
212 #define I2O_SIZE_8192 (5 << 10)
213 #define I2O_SIZE_16384 (6 << 10)
214 #define I2O_SIZE_32768 (7 << 10)
215 #define ROM_WIDTH_8 (3 << 14)
216 #define ROM_WIDTH_16 (1 << 14)
217 #define ROM_WIDTH_32 (2 << 14)
218 #define ROM_ACCESS_TIME_SHIFT 16
219 #define ROM_BURST_TIME_SHIFT 20
220 #define ROM_TRISTATE_TIME_SHIFT 24
221 #define XCS_DIRECTION_SHIFT 28
222 #define PCI_CENTRAL_FUNCTION (1 << 31)
223
224 #define PCI_ADDRESS_EXTENSION 0x140
225 #define PREFETCHABLE_MEM_RANGE 0x144
226
227 /* XBUS / PCI Arbiter registers */
228
229 #define XBUS_CYCLE_ARBITER 0x148
230 #define XBUS_CYCLE_0_SHIFT 0
231 #define XBUS_CYCLE_1_SHIFT 3
232 #define XBUS_CYCLE_2_SHIFT 6
233 #define XBUS_CYCLE_3_SHIFT 9
234 #define XBUS_CYCLE_STROBE_SHIFT 12
235 #define XBUS_PCI_ARBITER (1 << 23)
236 #define XBUS_INT_IN_L0_LOW 0
237 #define XBUS_INT_IN_L0_HIGH (1 << 24)
238 #define XBUS_INT_IN_L1_LOW 0
239 #define XBUS_INT_IN_L1_HIGH (1 << 25)
240 #define XBUS_INT_IN_L2_LOW 0
241 #define XBUS_INT_IN_L2_HIGH (1 << 26)
242 #define XBUS_INT_IN_L3_LOW 0
243 #define XBUS_INT_IN_L3_HIGH (1 << 27)
244 #define XBUS_INT_XCS0_LOW 0
245 #define XBUS_INT_XCS0_HIGH (1 << 28)
246 #define XBUS_INT_XCS1_LOW 0
247 #define XBUS_INT_XCS1_HIGH (1 << 29)
248 #define XBUS_INT_XCS2_LOW 0
249 #define XBUS_INT_XCS2_HIGH (1 << 30)
250 #define XBUS_PCI_INT_REQUEST (1 << 31)
251
252 #define XBUS_IO_STROBE_MASK 0x14C
253 #define XBUS_IO_STROBE_0_SHIFT 0
254 #define XBUS_IO_STROBE_2_SHIFT 8
255 #define XBUS_IO_STROBE_3_SHIFT 16
256 #define XBUS_IO_STROBE_4_SHIFT 24
257
258 #define DOORBELL_PCI_MASK 0x150
259 #define DOORBELL_SA_MASK 0x154
260
261 /* UART registers */
262
263 #define UART_DATA 0x160
264 #define UART_RX_STAT 0x164
265 #define UART_PARITY_ERROR 0x01
266 #define UART_FRAME_ERROR 0x02
267 #define UART_OVERRUN_ERROR 0x04
268 #define UART_RX_ERROR (UART_PARITY_ERROR | UART_FRAME_ERROR \
269 | UART_OVERRUN_ERROR)
270 #define UART_H_UBRLCR 0x168
271 #define UART_BREAK 0x01
272 #define UART_PARITY_ENABLE 0x02
273 #define UART_ODD_PARITY 0x00
274 #define UART_EVEN_PARITY 0x04
275 #define UART_STOP_BITS_1 0x00
276 #define UART_STOP_BITS_2 0x08
277 #define UART_ENABLE_FIFO 0x10
278 #define UART_DATA_BITS_5 0x00
279 #define UART_DATA_BITS_6 0x20
280 #define UART_DATA_BITS_7 0x40
281 #define UART_DATA_BITS_8 0x60
282 #define UART_M_UBRLCR 0x16C
283 #define UART_L_UBRLCR 0x170
284 #define UART_BRD(fclk, x) (((fclk) / 4 / 16 / x) - 1)
285
286 #define UART_CONTROL 0x174
287 #define UART_ENABLE 0x01
288 #define UART_SIR_ENABLE 0x02
289 #define UART_IRDA_ENABLE 0x04
290 #define UART_FLAGS 0x178
291 #define UART_TX_BUSY 0x08
292 #define UART_RX_FULL 0x10
293 #define UART_TX_EMPTY 0x20
294
295 /* Interrupt numbers for IRQ and FIQ registers */
296
297 #define IRQ_RESERVED0 0x00
298 #define IRQ_SOFTINT 0x01
299 #define IRQ_SERIAL_RX 0x02
300 #define IRQ_SERIAL_TX 0x03
301 #define IRQ_TIMER_1 0x04
302 #define IRQ_TIMER_2 0x05
303 #define IRQ_TIMER_3 0x06
304 #define IRQ_TIMER_4 0x07
305 #define IRQ_IN_L0 0x08
306 #define IRQ_IN_L1 0x09
307 #define IRQ_IN_L2 0x0A
308 #define IRQ_IN_L3 0x0B
309 #define IRQ_XCS_L0 0x0C
310 #define IRQ_XCS_L1 0x0D
311 #define IRQ_XCS_L2 0x0E
312 #define IRQ_DOORBELL 0x0F
313 #define IRQ_DMA_1 0x10
314 #define IRQ_DMA_2 0x11
315 #define IRQ_PCI 0x12
316 #define IRQ_PMCSR 0x13
317 #define IRQ_RESERVED1 0x14
318 #define IRQ_RESERVED2 0x15
319 #define IRQ_BIST 0x16
320 #define IRQ_SERR 0x17
321 #define IRQ_SDRAM_PARITY 0x18
322 #define IRQ_I2O 0x19
323 #define IRQ_RESERVED3 0x1A
324 #define IRQ_DISCARD_TIMER 0x1B
325 #define IRQ_DATA_PARITY 0x1C
326 #define IRQ_MASTER_ABORT 0x1D
327 #define IRQ_TARGET_ABORT 0x1E
328 #define IRQ_PARITY 0x1F
329
330 /* IRQ and FIQ status / enable registers */
331
332 #define IRQ_STATUS 0x180
333 #define IRQ_RAW_STATUS 0x184
334 #define IRQ_ENABLE 0x188
335 #define IRQ_ENABLE_SET 0x188
336 #define IRQ_ENABLE_CLEAR 0x18c
337 #define IRQ_SOFT 0x190
338
339 #define FIQ_STATUS 0x280
340 #define FIQ_RAW_STATUS 0x284
341 #define FIQ_ENABLE 0x288
342 #define FIQ_ENABLE_SET 0x288
343 #define FIQ_ENABLE_CLEAR 0x28c
344 #define FIQ_SOFT 0x290
345
346 /* Timer registers */
347
348 /* Relative offsets and bases */
349
350 #define TIMER_LOAD 0x00
351 #define TIMER_VALUE 0x04
352 #define TIMER_CONTROL 0x08
353 #define TIMER_CLEAR 0x0C
354 #define TIMER_1_BASE 0x300
355 #define TIMER_2_BASE 0x320
356 #define TIMER_3_BASE 0x340
357 #define TIMER_4_BASE 0x360
358
359 /* Control register bits */
360
361 #define TIMER_FCLK 0x00
362 #define TIMER_FCLK_16 0x04
363 #define TIMER_FCLK_256 0x08
364 #define TIMER_EXTERNAL 0x0C
365 #define TIMER_MODE_FREERUN 0x00
366 #define TIMER_MODE_PERIODIC 0x40
367 #define TIMER_ENABLE 0x80
368
369 /* Maximum timer value */
370
371 #define TIMER_MAX_VAL 0x00FFFFFF
372
373 /* Specific registers */
374
375 #define TIMER_1_LOAD 0x300
376 #define TIMER_1_VALUE 0x304
377 #define TIMER_1_CONTROL 0x308
378 #define TIMER_1_CLEAR 0x30C
379 #define TIMER_2_LOAD 0x320
380 #define TIMER_2_VALUE 0x324
381 #define TIMER_2_CONTROL 0x328
382 #define TIMER_2_CLEAR 0x32C
383 #define TIMER_3_LOAD 0x340
384 #define TIMER_3_VALUE 0x344
385 #define TIMER_3_CONTROL 0x348
386 #define TIMER_3_CLEAR 0x34C
387 #define TIMER_4_LOAD 0x360
388 #define TIMER_4_VALUE 0x364
389 #define TIMER_4_CONTROL 0x368
390 #define TIMER_4_CLEAR 0x36C
391
392 /* Miscellaneous definitions */
393
394 #ifndef FCLK
395 #define FCLK 50000000
396 #endif
397
398 #endif /* DC21285REG_H */

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