/[gxemul]/trunk/src/include/cpuregs.h
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Revision 4 - (show annotations)
Mon Oct 8 16:18:00 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 26448 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============


1 /* gxemul: $Id: cpuregs.h,v 1.3 2005/03/05 12:34:02 debug Exp $ */
2 /* $NetBSD: cpuregs.h,v 1.50 2002/03/13 13:18:58 simonb Exp $ */
3
4 /*
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * Ralph Campbell and Rick Macklem.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * @(#)machConst.h 8.1 (Berkeley) 6/10/93
40 *
41 * machConst.h --
42 *
43 * Machine dependent constants.
44 *
45 * Copyright (C) 1989 Digital Equipment Corporation.
46 * Permission to use, copy, modify, and distribute this software and
47 * its documentation for any purpose and without fee is hereby granted,
48 * provided that the above copyright notice appears in all copies.
49 * Digital Equipment Corporation makes no representations about the
50 * suitability of this software for any purpose. It is provided "as is"
51 * without express or implied warranty.
52 *
53 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
54 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
55 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
56 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
57 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
58 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
59 */
60
61 #ifndef _MIPS_CPUREGS_H_
62 #define _MIPS_CPUREGS_H_
63
64 /* #include <sys/cdefs.h> */ /* For __CONCAT() */
65 /*
66 * Address space.
67 * 32-bit mips CPUS partition their 32-bit address space into four segments:
68 *
69 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
70 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
71 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
72 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
73 *
74 * mips1 physical memory is limited to 512Mbytes, which is
75 * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
76 * Caching of mapped addresses is controlled by bits in the TLB entry.
77 */
78
79 #define MIPS_KUSEG_START 0x0
80 #define MIPS_KSEG0_START 0x80000000
81 #define MIPS_KSEG1_START 0xa0000000
82 #define MIPS_KSEG2_START 0xc0000000
83 #define MIPS_MAX_MEM_ADDR 0xbe000000
84 #define MIPS_RESERVED_ADDR 0xbfc80000
85
86 #define MIPS_PHYS_MASK 0x1fffffff
87
88 #define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK)
89 #define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START)
90 #define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK)
91 #define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
92
93 /* Map virtual address to index in mips3 r4k virtually-indexed cache */
94 #define MIPS3_VA_TO_CINDEX(x) \
95 ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
96
97 #define MIPS_PHYS_TO_XKPHYS(cca,x) \
98 ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
99 #define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL)
100
101 /* CPU dependent mtc0 hazard hook */
102 #define COP0_SYNC /* nothing */
103
104 /*
105 * The bits in the cause register.
106 *
107 * Bits common to r3000 and r4000:
108 *
109 * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
110 * MIPS_CR_COP_ERR Coprocessor error.
111 * MIPS_CR_IP Interrupt pending bits defined below.
112 * (same meaning as in CAUSE register).
113 * MIPS_CR_EXC_CODE The exception type (see exception codes below).
114 *
115 * Differences:
116 * r3k has 4 bits of execption type, r4k has 5 bits.
117 */
118 #define MIPS_CR_BR_DELAY 0x80000000
119 #define MIPS_CR_COP_ERR 0x30000000
120 #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
121 #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
122 #define MIPS_CR_IP 0x0000FF00
123 #define MIPS_CR_EXC_CODE_SHIFT 2
124
125 /*
126 * The bits in the status register. All bits are active when set to 1.
127 *
128 * R3000 status register fields:
129 * MIPS_SR_CO_USABILITY Control the usability of the four coprocessors.
130 * MIPS_SR_BOOT_EXC_VEC Use alternate exception vectors.
131 * MIPS_SR_TLB_SHUTDOWN TLB disabled.
132 *
133 * MIPS_SR_INT_IE Master (current) interrupt enable bit.
134 *
135 * Differences:
136 * r3k has cache control is via frobbing SR register bits, whereas the
137 * r4k cache control is via explicit instructions.
138 * r3k has a 3-entry stack of kernel/user bits, whereas the
139 * r4k has kernel/supervisor/user.
140 */
141 #define MIPS_SR_COP_USABILITY 0xf0000000
142 #define MIPS_SR_COP_0_BIT 0x10000000
143 #define MIPS_SR_COP_1_BIT 0x20000000
144
145 /* r4k and r3k differences, see below */
146
147 #define MIPS_SR_BOOT_EXC_VEC 0x00400000
148 #define MIPS_SR_TLB_SHUTDOWN 0x00200000
149
150 /* r4k and r3k differences, see below */
151
152 #define MIPS_SR_INT_IE 0x00000001
153 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
154 /*#define MIPS_SR_INT_MASK 0x0000ff00*/
155
156
157 /*
158 * The R2000/R3000-specific status register bit definitions.
159 * all bits are active when set to 1.
160 *
161 * MIPS_SR_PARITY_ERR Parity error.
162 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
163 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
164 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
165 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
166 * Interrupt enable bits defined below.
167 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
168 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
169 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
170 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
171 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
172 */
173
174 #define MIPS1_PARITY_ERR 0x00100000
175 #define MIPS1_CACHE_MISS 0x00080000
176 #define MIPS1_PARITY_ZERO 0x00040000
177 #define MIPS1_SWAP_CACHES 0x00020000
178 #define MIPS1_ISOL_CACHES 0x00010000
179
180 #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
181 #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
182 #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
183 #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
184 #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
185
186 /* backwards compatibility */
187 #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
188 #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
189 #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
190 #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
191 #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
192
193 #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
194 #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
195 #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
196 #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
197 #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
198
199 /*
200 * R4000 status register bit definitons,
201 * where different from r2000/r3000.
202 */
203 #define MIPS3_SR_XX 0x80000000
204 #define MIPS3_SR_RP 0x08000000
205 #define MIPS3_SR_FR_32 0x04000000
206 #define MIPS3_SR_RE 0x02000000
207
208 #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
209 #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
210 #define MIPS3_SR_DIAG_BEV 0x00400000
211 #define MIPS3_SR_SOFT_RESET 0x00100000
212 #define MIPS3_SR_EIE 0x00100000 /* TX79/R5900 */
213 #define MIPS3_SR_DIAG_CH 0x00040000
214 #define MIPS3_SR_DIAG_CE 0x00020000
215 #define MIPS3_SR_DIAG_PE 0x00010000
216 #define MIPS3_SR_KX 0x00000080
217 #define MIPS3_SR_SX 0x00000040
218 #define MIPS3_SR_UX 0x00000020
219 #define MIPS3_SR_KSU_MASK 0x00000018
220 #define MIPS3_SR_KSU_USER 0x00000010
221 #define MIPS3_SR_KSU_SUPER 0x00000008
222 #define MIPS3_SR_KSU_KERNEL 0x00000000
223 #define MIPS3_SR_ERL 0x00000004
224 #define MIPS3_SR_EXL 0x00000002
225
226 #ifdef MIPS3_5900
227 #undef MIPS_SR_INT_IE
228 #define MIPS_SR_INT_IE 0x00010001 /* XXX */
229 #endif
230
231 #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
232 #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
233 #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
234 #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
235 #define MIPS_SR_KX MIPS3_SR_KX
236 #define MIPS_SR_SX MIPS3_SR_SX
237 #define MIPS_SR_UX MIPS3_SR_UX
238
239 #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
240 #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
241 #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
242 #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
243 #define MIPS_SR_ERL MIPS3_SR_ERL
244 #define MIPS_SR_EXL MIPS3_SR_EXL
245
246
247 /*
248 * The interrupt masks.
249 * If a bit in the mask is 1 then the interrupt is enabled (or pending).
250 */
251 #define MIPS_INT_MASK 0xff00
252 #define MIPS_INT_MASK_5 0x8000
253 #define MIPS_INT_MASK_4 0x4000
254 #define MIPS_INT_MASK_3 0x2000
255 #define MIPS_INT_MASK_2 0x1000
256 #define MIPS_INT_MASK_1 0x0800
257 #define MIPS_INT_MASK_0 0x0400
258 #define MIPS_HARD_INT_MASK 0xfc00
259 #define MIPS_SOFT_INT_MASK_1 0x0200
260 #define MIPS_SOFT_INT_MASK_0 0x0100
261
262 /*
263 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
264 * choose to enable this interrupt.
265 */
266 #if defined(MIPS3_ENABLE_CLOCK_INTR)
267 #define MIPS3_INT_MASK MIPS_INT_MASK
268 #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
269 #else
270 #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
271 #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
272 #endif
273
274 /*
275 * The bits in the context register.
276 */
277 #define MIPS1_CNTXT_PTE_BASE 0xFFE00000
278 #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
279
280 #define MIPS3_CNTXT_PTE_BASE 0xFF800000
281 #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
282
283 /*
284 * The bits in the MIPS3 config register.
285 *
286 * bit 0..5: R/W, Bit 6..31: R/O
287 */
288
289 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
290 #define MIPS3_CONFIG_K0_MASK 0x00000007
291
292 /*
293 * R/W Update on Store Conditional
294 * 0: Store Conditional uses coherency algorithm specified by TLB
295 * 1: Store Conditional uses cacheable coherent update on write
296 */
297 #define MIPS3_CONFIG_CU 0x00000008
298
299 #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
300 #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
301 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
302 (((config) & (bit)) ? 32 : 16)
303
304 #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
305 #define MIPS3_CONFIG_DC_SHIFT 6
306 #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
307 #define MIPS3_CONFIG_IC_SHIFT 9
308 #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
309 #ifdef MIPS3_4100 /* VR4100 core */
310 /* XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY */
311 #define MIPS3_CONFIG_CS 0x00001000 /* cache size mode indication*/
312 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, dummy, shift) \
313 ((((config)&MIPS3_CONFIG_CS)?0x400:0x1000) << (((config) & (mask)) >> (shift)))
314 #else
315 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
316 ((base) << (((config) & (mask)) >> (shift)))
317 #endif
318
319 /* Block ordering: 0: sequential, 1: sub-block */
320 #define MIPS3_CONFIG_EB 0x00002000
321
322 /* ECC mode - 0: ECC mode, 1: parity mode */
323 #define MIPS3_CONFIG_EM 0x00004000
324
325 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
326 #define MIPS3_CONFIG_BE 0x00008000
327
328 /* Dirty Shared coherency state - 0: enabled, 1: disabled */
329 #define MIPS3_CONFIG_SM 0x00010000
330
331 /* Secondary Cache - 0: present, 1: not present */
332 #define MIPS3_CONFIG_SC 0x00020000
333
334 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
335 #define MIPS3_CONFIG_EW_MASK 0x000c0000
336 #define MIPS3_CONFIG_EW_SHIFT 18
337
338 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
339 #define MIPS3_CONFIG_SW 0x00100000
340
341 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
342 #define MIPS3_CONFIG_SS 0x00200000
343
344 /* Secondary Cache line size */
345 #define MIPS3_CONFIG_SB_MASK 0x00c00000
346 #define MIPS3_CONFIG_SB_SHIFT 22
347 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
348 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
349
350 /* Write back data rate */
351 #define MIPS3_CONFIG_EP_MASK 0x0f000000
352 #define MIPS3_CONFIG_EP_SHIFT 24
353
354 /* System clock ratio - this value is CPU dependent */
355 #define MIPS3_CONFIG_EC_MASK 0x70000000
356 #define MIPS3_CONFIG_EC_SHIFT 28
357
358 /* Master-Checker Mode - 1: enabled */
359 #define MIPS3_CONFIG_CM 0x80000000
360
361 /*
362 * Location of exception vectors.
363 *
364 * Common vectors: reset and UTLB miss.
365 */
366 #define MIPS_RESET_EXC_VEC 0xBFC00000
367 #define MIPS_UTLB_MISS_EXC_VEC 0x80000000
368
369 /*
370 * MIPS-1 general exception vector (everything else)
371 */
372 #define MIPS1_GEN_EXC_VEC 0x80000080
373
374 /*
375 * MIPS-III exception vectors
376 */
377 #define MIPS3_XTLB_MISS_EXC_VEC 0x80000080
378 #define MIPS3_CACHE_ERR_EXC_VEC 0x80000100
379 #define MIPS3_GEN_EXC_VEC 0x80000180
380
381 /*
382 * TX79 (R5900) exception vectors
383 */
384 #define MIPS_R5900_COUNTER_EXC_VEC 0x80000080
385 #define MIPS_R5900_DEBUG_EXC_VEC 0x80000100
386
387 /*
388 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
389 */
390 #define MIPS3_INTR_EXC_VEC 0x80000200
391
392 /*
393 * Coprocessor 0 registers:
394 *
395 * v--- width for mips I,III,32,64
396 * (3=32bit, 6=64bit, i=impl dep)
397 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index.
398 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random.
399 * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low.
400 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
401 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
402 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
403 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
404 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
405 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
406 * 9 MIPS_COP_0_COUNT .333 Count register.
407 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
408 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
409 * 12 MIPS_COP_0_STATUS 3333 Status register.
410 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
411 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
412 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
413 * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
414 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
415 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
416 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
417 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
418 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
419 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
420 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
421 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
422 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
423 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
424 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
425 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
426 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
427 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
428 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
429 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
430 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
431 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
432 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
433 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
434 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
435 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
436 */
437 #ifdef _LOCORE
438 #define _(n) __CONCAT($,n)
439 #else
440 #define _(n) n
441 #endif
442 #define MIPS_COP_0_TLB_INDEX _(0)
443 #define MIPS_COP_0_TLB_RANDOM _(1)
444 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
445
446 #define MIPS_COP_0_TLB_CONTEXT _(4)
447 /* $5 and $6 new with MIPS-III */
448 #define MIPS_COP_0_BAD_VADDR _(8)
449 #define MIPS_COP_0_TLB_HI _(10)
450 #define MIPS_COP_0_STATUS_REG _(12)
451 #define MIPS_COP_0_CAUSE_REG _(13)
452 #define MIPS_COP_0_STATUS _(12)
453 #define MIPS_COP_0_CAUSE _(13)
454 #define MIPS_COP_0_EXC_PC _(14)
455 #define MIPS_COP_0_PRID _(15)
456
457
458 /* MIPS-I */
459 #define MIPS_COP_0_TLB_LOW _(2)
460
461 /* MIPS-III */
462 #define MIPS_COP_0_TLB_LO0 _(2)
463 #define MIPS_COP_0_TLB_LO1 _(3)
464
465 #define MIPS_COP_0_TLB_PG_MASK _(5)
466 #define MIPS_COP_0_TLB_WIRED _(6)
467
468 #define MIPS_COP_0_COUNT _(9)
469 #define MIPS_COP_0_COMPARE _(11)
470
471 #define MIPS_COP_0_CONFIG _(16)
472 #define MIPS_COP_0_LLADDR _(17)
473 #define MIPS_COP_0_WATCH_LO _(18)
474 #define MIPS_COP_0_WATCH_HI _(19)
475 #define MIPS_COP_0_TLB_XCONTEXT _(20)
476 #define MIPS_COP_0_ECC _(26)
477 #define MIPS_COP_0_CACHE_ERR _(27)
478 #define MIPS_COP_0_TAG_LO _(28)
479 #define MIPS_COP_0_TAG_HI _(29)
480 #define MIPS_COP_0_ERROR_PC _(30)
481
482 /* MIPS32/64 */
483 #define MIPS_COP_0_DEBUG _(23)
484 #define MIPS_COP_0_DEPC _(24)
485 #define MIPS_COP_0_PERFCNT _(25)
486 #define MIPS_COP_0_DATA_LO _(28)
487 #define MIPS_COP_0_DATA_HI _(29)
488 #define MIPS_COP_0_DESAVE _(31)
489
490 /*
491 * Values for the code field in a break instruction.
492 */
493 #define MIPS_BREAK_INSTR 0x0000000d
494 #define MIPS_BREAK_VAL_MASK 0x03ff0000
495 #define MIPS_BREAK_VAL_SHIFT 16
496 #define MIPS_BREAK_KDB_VAL 512
497 #define MIPS_BREAK_SSTEP_VAL 513
498 #define MIPS_BREAK_BRKPT_VAL 514
499 #define MIPS_BREAK_SOVER_VAL 515
500 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
501 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
502 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
503 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
504 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
505 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
506 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
507 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
508
509 /*
510 * Mininum and maximum cache sizes.
511 */
512 #define MIPS_MIN_CACHE_SIZE (16 * 1024)
513 #define MIPS_MAX_CACHE_SIZE (256 * 1024)
514 #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
515
516 /*
517 * The floating point version and status registers.
518 */
519 #define MIPS_FPU_ID $0
520 #define MIPS_FPU_CSR $31
521
522 /*
523 * The floating point coprocessor status register bits.
524 */
525 #define MIPS_FPU_ROUNDING_BITS 0x00000003
526 #define MIPS_FPU_ROUND_RN 0x00000000
527 #define MIPS_FPU_ROUND_RZ 0x00000001
528 #define MIPS_FPU_ROUND_RP 0x00000002
529 #define MIPS_FPU_ROUND_RM 0x00000003
530 #define MIPS_FPU_STICKY_BITS 0x0000007c
531 #define MIPS_FPU_STICKY_INEXACT 0x00000004
532 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
533 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010
534 #define MIPS_FPU_STICKY_DIV0 0x00000020
535 #define MIPS_FPU_STICKY_INVALID 0x00000040
536 #define MIPS_FPU_ENABLE_BITS 0x00000f80
537 #define MIPS_FPU_ENABLE_INEXACT 0x00000080
538 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
539 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
540 #define MIPS_FPU_ENABLE_DIV0 0x00000400
541 #define MIPS_FPU_ENABLE_INVALID 0x00000800
542 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000
543 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
544 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
545 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
546 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000
547 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000
548 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
549 #define MIPS_FPU_COND_BIT 0x00800000
550 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
551 #define MIPS1_FPC_MBZ_BITS 0xff7c0000
552 #define MIPS3_FPC_MBZ_BITS 0xfe7c0000
553
554
555 /*
556 * Constants to determine if have a floating point instruction.
557 */
558 #define MIPS_OPCODE_SHIFT 26
559 #define MIPS_OPCODE_C1 0x11
560 #define MIPS_OPCODE_LWC1 0x31
561 #define MIPS_OPCODE_LDC1 0x35
562 #define MIPS_OPCODE_SWC1 0x39
563 #define MIPS_OPCODE_SDC1 0x3d
564
565
566 /*
567 * The low part of the TLB entry.
568 */
569 #define MIPS1_TLB_PFN 0xfffff000
570 #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
571 #define MIPS1_TLB_DIRTY_BIT 0x00000400
572 #define MIPS1_TLB_VALID_BIT 0x00000200
573 #define MIPS1_TLB_GLOBAL_BIT 0x00000100
574
575 #define MIPS3_TLB_PFN 0x3fffffc0
576 #define MIPS3_TLB_ATTR_MASK 0x00000038
577 #define MIPS3_TLB_ATTR_SHIFT 3
578 #define MIPS3_TLB_DIRTY_BIT 0x00000004
579 #define MIPS3_TLB_VALID_BIT 0x00000002
580 #define MIPS3_TLB_GLOBAL_BIT 0x00000001
581
582 #define MIPS1_TLB_PHYS_PAGE_SHIFT 12
583 #define MIPS3_TLB_PHYS_PAGE_SHIFT 6
584 #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
585 #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
586 #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
587 #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
588
589 /*
590 * MIPS3_TLB_ATTR values - coherency algorithm:
591 * 0: cacheable, noncoherent, write-through, no write allocate
592 * 1: cacheable, noncoherent, write-through, write allocate
593 * 2: uncached
594 * 3: cacheable, noncoherent, write-back (noncoherent)
595 * 4: cacheable, coherent, write-back, exclusive (exclusive)
596 * 5: cacheable, coherent, write-back, exclusive on write (sharable)
597 * 6: cacheable, coherent, write-back, update on write (update)
598 * 7: uncached, accelerated (gather STORE operations)
599 */
600 #define MIPS3_TLB_ATTR_WT 0 /* IDT */
601 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
602 #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
603 #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
604 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
605 #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
606 #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
607 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */
608
609
610 /*
611 * The high part of the TLB entry.
612 */
613 #define MIPS1_TLB_VPN 0xfffff000
614 #define MIPS1_TLB_PID 0x00000fc0
615 #define MIPS1_TLB_PID_SHIFT 6
616
617 #define MIPS3_TLB_VPN2 0xffffe000
618 #define MIPS3_TLB_ASID 0x000000ff
619
620 #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
621 #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
622 #define MIPS3_TLB_PID MIPS3_TLB_ASID
623 #define MIPS_TLB_VIRT_PAGE_SHIFT 12
624
625 /*
626 * r3000: shift count to put the index in the right spot.
627 */
628 #define MIPS1_TLB_INDEX_SHIFT 8
629
630 /*
631 * The first TLB that write random hits.
632 */
633 #define MIPS1_TLB_FIRST_RAND_ENTRY 8
634 #define MIPS3_TLB_WIRED_UPAGES 1
635
636 /*
637 * The number of process id entries.
638 */
639 #define MIPS1_TLB_NUM_PIDS 64
640 #define MIPS3_TLB_NUM_ASIDS 256
641
642 /*
643 * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
644 */
645
646 /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
647
648 #if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
649 && defined(MIPS1) /* XXX simonb must be neater! */
650 #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
651 #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
652 #endif
653
654 #if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
655 && !defined(MIPS1) /* XXX simonb must be neater! */
656 #define MIPS_TLB_PID_SHIFT 0
657 #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
658 #endif
659
660
661 #if !defined(MIPS_TLB_PID_SHIFT)
662 #define MIPS_TLB_PID_SHIFT \
663 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
664
665 #define MIPS_TLB_NUM_PIDS \
666 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
667 #endif
668
669 /*
670 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
671 */
672 #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */
673 #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */
674 #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */
675 #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */
676 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */
677 #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */
678 #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */
679 #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */
680 #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */
681 #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */
682 #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */
683 #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */
684 #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */
685 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
686 #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */
687 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
688 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
689 #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */
690 #define MIPS_R4650 0x22 /* QED R4650 ISA III */
691 #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */
692 #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */
693 #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */
694 #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */
695 #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */
696 #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */
697 #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */
698 #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */
699 #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */
700 #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */
701
702 /*
703 * CPU revision IDs for some prehistoric processors.
704 */
705
706 /* For MIPS_R3000 */
707 #define MIPS_REV_R3000 0x20
708 #define MIPS_REV_R3000A 0x30
709
710 /* For MIPS_TX3900 */
711 #define MIPS_REV_TX3912 0x10
712 #define MIPS_REV_TX3922 0x30
713 #define MIPS_REV_TX3927 0x40
714
715 /* For MIPS_R4000 */
716 #define MIPS_REV_R4000_A 0x00
717 #define MIPS_REV_R4000_B 0x30
718 #define MIPS_REV_R4400_A 0x40
719 #define MIPS_REV_R4400_B 0x50
720 #define MIPS_REV_R4400_C 0x60
721
722 /*
723 * CPU processor revision IDs for company ID == 1 (MIPS)
724 */
725 #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */
726 #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */
727 #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */
728 #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */
729
730 /*
731 * CPU processor revision IDs for company ID == 3 (Alchemy)
732 */
733 #define MIPS_AU1000_R1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */
734 #define MIPS_AU1000_R2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */
735
736 /*
737 * CPU processor revision IDs for company ID == 4 (SiByte)
738 */
739 #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */
740
741 /*
742 * CPU processor revision IDs for company ID == 5 (SandCraft)
743 */
744 #define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */
745
746 /*
747 * FPU processor revision ID
748 */
749 #define MIPS_SOFT 0x00 /* Software emulation ISA I */
750 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
751 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
752 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
753 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
754 #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */
755 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
756 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
757
758 #ifdef ENABLE_MIPS_TX3900
759 #include <mips/r3900regs.h>
760 #endif
761 #ifdef MIPS3_5900
762 #include <mips/r5900regs.h>
763 #endif
764
765 #endif /* _MIPS_CPUREGS_H_ */

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