src/include/cpu_x86.h

#ifndef CPU_X86_H
#define CPU_X86_H

/*
 *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_x86.h,v 1.48 2006/06/24 21:47:24 debug Exp $
 *
 *  x86 (including AMD64) cpu dependent stuff.
 */

#include "misc.h"


struct cpu_family;

#define N_X86_REGS              16

#define x86_reg_names           {                       \
        "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \
        "08", "09", "10", "11", "12", "13", "14", "15" }
#define x86_reg_names_bytes     {                       \
        "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" }

#define X86_R_AX        0
#define X86_R_CX        1
#define X86_R_DX        2
#define X86_R_BX        3
#define X86_R_SP        4
#define X86_R_BP        5
#define X86_R_SI        6
#define X86_R_DI        7

#define N_X86_SEGS              8
/*  (All of these 8 are not actually used.)  */

#define X86_S_ES        0
#define X86_S_CS        1
#define X86_S_SS        2
#define X86_S_DS        3
#define X86_S_FS        4
#define X86_S_GS        5

#define x86_seg_names   { "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7" }

#define N_X86_CREGS             8

#define N_X86_DREGS             8

#define x86_cond_names  { "o", "b", "z", "be", "s", "p", "l", "le" }
#define N_X86_CONDS             8

#define X86_MODEL_8086          1
#define X86_MODEL_80286         2
#define X86_MODEL_80386         3
#define X86_MODEL_80486         4
#define X86_MODEL_PENTIUM       5
#define X86_MODEL_AMD64         6

struct x86_model {
        int             model_number;
        char            *name;
};

#define x86_models {                                                    \
        { X86_MODEL_8086, "8086" },                                     \
        { X86_MODEL_80286, "80286" },                                   \
        { X86_MODEL_80386, "80386" },                                   \
        { X86_MODEL_80486, "80486" },                                   \
        { X86_MODEL_PENTIUM, "PENTIUM" },                               \
        { X86_MODEL_AMD64, "AMD64" },                                   \
        { 0, NULL }                                                     \
        }

#define X86_N_IC_ARGS                   3
#define X86_INSTR_ALIGNMENT_SHIFT       0
#define X86_IC_ENTRIES_SHIFT            12
#define X86_IC_ENTRIES_PER_PAGE         (1 << X86_IC_ENTRIES_SHIFT)
#define X86_PC_TO_IC_ENTRY(a)           ((a) & (X86_IC_ENTRIES_PER_PAGE-1))
#define X86_ADDR_TO_PAGENR(a)           ((a) >> X86_IC_ENTRIES_SHIFT)

#define X86_L2N                 17
#define X86_L3N                 18

DYNTRANS_MISC_DECLARATIONS(x86,X86,uint64_t)
DYNTRANS_MISC64_DECLARATIONS(x86,X86,uint8_t)

#define X86_MAX_VPH_TLB_ENTRIES         128

struct descriptor_cache {
        int             valid;
        int             default_op_size;
        int             access_rights;
        int             descr_type;
        int             readable;
        int             writable;
        int             granularity;
        uint64_t        base;
        uint64_t        limit;
};


struct x86_cpu {
        struct x86_model model;

        int             halted;
        int             interrupt_asserted;

        int             cursegment;     /*  NOTE: 0..N_X86_SEGS-1  */
        int             seg_override;   /*  0 or 1  */

        uint64_t        tsc;            /*  time stamp counter  */

        uint64_t        gdtr;           /*  global descriptor table */
        uint32_t        gdtr_limit;
        uint64_t        idtr;           /*  interrupt descriptor table  */
        uint32_t        idtr_limit;

        uint16_t        tr;             /*  task register  */
        uint64_t        tr_base;
        uint32_t        tr_limit;
        uint16_t        ldtr;           /*  local descriptor table register  */
        uint64_t        ldtr_base;
        uint32_t        ldtr_limit;

        uint64_t        rflags;
        uint64_t        cr[N_X86_CREGS];        /*  control registers  */
        uint64_t        dr[N_X86_DREGS];        /*  debug registers  */

        uint16_t        s[N_X86_SEGS];          /*  segment selectors  */
        struct descriptor_cache descr_cache[N_X86_SEGS];

        uint64_t        r[N_X86_REGS];          /*  GPRs  */

        /*  FPU:  */
        uint16_t        fpu_sw;         /*  status word  */
        uint16_t        fpu_cw;         /*  control word  */

        /*  MSRs:  */
        uint64_t        efer;


        /*
         *  Instruction translation cache and Virtual->Physical->Host
         *  address translation:
         */
        DYNTRANS_ITC(x86)
        VPH_TLBS(x86,X86)
        VPH32(x86,X86,uint64_t,uint8_t)
        VPH64(x86,X86,uint8_t)
};


#define X86_FLAGS_CF    (1)             /*  Carry Flag  */
#define X86_FLAGS_PF    (4)             /*  Parity Flag  */
#define X86_FLAGS_AF    (16)            /*  Adjust/AuxilaryCarry Flag  */
#define X86_FLAGS_ZF    (64)            /*  Zero Flag  */
#define X86_FLAGS_SF    (128)           /*  Sign Flag  */
#define X86_FLAGS_TF    (256)           /*  Trap Flag  */
#define X86_FLAGS_IF    (512)           /*  Interrupt Enable Flag  */
#define X86_FLAGS_DF    (1024)          /*  Direction Flag  */
#define X86_FLAGS_OF    (2048)          /*  Overflow Flag  */
/*  Bits 12 and 13 are I/O Privilege Level  */
#define X86_FLAGS_NT    (1<<14)         /*  Nested Task Flag  */
#define X86_FLAGS_RF    (1<<16)         /*  Resume Flag  */
#define X86_FLAGS_VM    (1<<17)         /*  VM86 Flag  */
#define X86_FLAGS_AC    (1<<18)         /*  Alignment Check  */
#define X86_FLAGS_VIF   (1<<19)         /*  ?  */
#define X86_FLAGS_VIP   (1<<20)         /*  ?  */
#define X86_FLAGS_ID    (1<<21)         /*  CPUID present  */

#define X86_CR0_PE      0x00000001      /*  Protection Enable  */
#define X86_CR0_MP      0x00000002
#define X86_CR0_EM      0x00000004
#define X86_CR0_TS      0x00000008
#define X86_CR0_ET      0x00000010
#define X86_CR0_NE      0x00000020
#define X86_CR0_WP      0x00010000
#define X86_CR0_AM      0x00040000
#define X86_CR0_NW      0x20000000
#define X86_CR0_CD      0x40000000
#define X86_CR0_PG      0x80000000      /*  Paging Enable  */

#define X86_CR4_OSXMEX  0x00000400
#define X86_CR4_OSFXSR  0x00000200
#define X86_CR4_PCE     0x00000100
#define X86_CR4_PGE     0x00000080
#define X86_CR4_MCE     0x00000040
#define X86_CR4_PAE     0x00000020
#define X86_CR4_PSE     0x00000010
#define X86_CR4_DE      0x00000008
#define X86_CR4_TSD     0x00000004      /*  Time Stamp Disable  */
#define X86_CR4_PVI     0x00000002
#define X86_CR4_VME     0x00000001

/*  EFER bits:  */
#define X86_EFER_FFXSR  0x00004000
#define X86_EFER_LMSLE  0x00002000
#define X86_EFER_NXE    0x00000800
#define X86_EFER_LMA    0x00000400
#define X86_EFER_LME    0x00000100      /*  Long Mode (64-bit)  */
#define X86_EFER_SCE    0x00000001

/*  CPUID feature bits:  */
#define X86_CPUID_ECX_ETPRD     0x00004000
#define X86_CPUID_ECX_CX16      0x00002000      /*  cmpxchg16b  */
#define X86_CPUID_ECX_CID       0x00000400
#define X86_CPUID_ECX_TM2       0x00000100
#define X86_CPUID_ECX_EST       0x00000080
#define X86_CPUID_ECX_DSCPL     0x00000010
#define X86_CPUID_ECX_MON       0x00000004
#define X86_CPUID_ECX_SSE3      0x00000001
#define X86_CPUID_EDX_PBE       0x80000000      /*  pending break event  */
#define X86_CPUID_EDX_IA64      0x40000000
#define X86_CPUID_EDX_TM1       0x20000000      /*  thermal interrupt  */
#define X86_CPUID_EDX_HTT       0x10000000      /*  hyper threading  */
#define X86_CPUID_EDX_SS        0x08000000      /*  self-snoop  */
#define X86_CPUID_EDX_SSE2      0x04000000
#define X86_CPUID_EDX_SSE       0x02000000
#define X86_CPUID_EDX_FXSR      0x01000000
#define X86_CPUID_EDX_MMX       0x00800000
#define X86_CPUID_EDX_ACPI      0x00400000
#define X86_CPUID_EDX_DTES      0x00200000
#define X86_CPUID_EDX_CLFL      0x00080000
#define X86_CPUID_EDX_PSN       0x00040000
#define X86_CPUID_EDX_PSE36     0x00020000
#define X86_CPUID_EDX_PAT       0x00010000
#define X86_CPUID_EDX_CMOV      0x00008000
#define X86_CPUID_EDX_MCA       0x00004000
#define X86_CPUID_EDX_PGE       0x00002000      /*  global bit in PDE/PTE  */
#define X86_CPUID_EDX_MTRR      0x00001000
#define X86_CPUID_EDX_SEP       0x00000800      /*  sysenter/sysexit  */
#define X86_CPUID_EDX_APIC      0x00000200
#define X86_CPUID_EDX_CX8       0x00000100      /*  cmpxchg8b  */
#define X86_CPUID_EDX_MCE       0x00000080
#define X86_CPUID_EDX_PAE       0x00000040
#define X86_CPUID_EDX_MSR       0x00000020
#define X86_CPUID_EDX_TSC       0x00000010
#define X86_CPUID_EDX_PSE       0x00000008
#define X86_CPUID_EDX_DE        0x00000004
#define X86_CPUID_EDX_VME       0x00000002
#define X86_CPUID_EDX_FPU       0x00000001

/*  Extended CPUID flags:  */
#define X86_CPUID_EXT_ECX_CR8D  0x00000010
#define X86_CPUID_EXT_ECX_CMP   0x00000002
#define X86_CPUID_EXT_ECX_AHF64 0x00000001
#define X86_CPUID_EXT_EDX_LM    0x20000000      /*  AMD64 Long Mode  */
#define X86_CPUID_EXT_EDX_FFXSR 0x02000000
/*  TODO: Many bits are duplicated in the Extended CPUID bits!  */

#define X86_IO_BASE     0x1000000000ULL

/*  Privilege level in the lowest 2 bits of a selector:  */
#define X86_PL_MASK             0x0003
#define X86_RING0               0
#define X86_RING1               1
#define X86_RING2               2
#define X86_RING3               3

#define DESCR_TYPE_CODE         1
#define DESCR_TYPE_DATA         2


#define LONG_MODE               (cpu->cd.x86.efer & X86_EFER_LME)
#define PROTECTED_MODE          (cpu->cd.x86.cr[0] & X86_CR0_PE)
#define REAL_MODE               (!PROTECTED_MODE)


/*  cpu_x86.c:  */
void reload_segment_descriptor(struct cpu *cpu, int segnr, int selector,
        uint64_t *curpcp);
int x86_interrupt(struct cpu *cpu, int nr, int errcode);
int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
void x86_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void x8632_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void x86_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void x8632_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void x86_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
void x8632_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
void x86_init_64bit_dummy_tables(struct cpu *cpu);
int x86_cpu_family_init(struct cpu_family *);


/*  memory_x86.c:  */
int x86_translate_v2p(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);

#endif  /*  CPU_X86_H  */
1	#ifndef CPU_X86_H
2	#define CPU_X86_H
3
4	/*
5	* Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu_x86.h,v 1.48 2006/06/24 21:47:24 debug Exp $
32	*
33	* x86 (including AMD64) cpu dependent stuff.
34	*/
35
36	#include "misc.h"
37
38
39	struct cpu_family;
40
41	#define N_X86_REGS 16
42
43	#define x86_reg_names { \
44	"ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \
45	"08", "09", "10", "11", "12", "13", "14", "15" }
46	#define x86_reg_names_bytes { \
47	"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" }
48
49	#define X86_R_AX 0
50	#define X86_R_CX 1
51	#define X86_R_DX 2
52	#define X86_R_BX 3
53	#define X86_R_SP 4
54	#define X86_R_BP 5
55	#define X86_R_SI 6
56	#define X86_R_DI 7
57
58	#define N_X86_SEGS 8
59	/* (All of these 8 are not actually used.) */
60
61	#define X86_S_ES 0
62	#define X86_S_CS 1
63	#define X86_S_SS 2
64	#define X86_S_DS 3
65	#define X86_S_FS 4
66	#define X86_S_GS 5
67
68	#define x86_seg_names { "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7" }
69
70	#define N_X86_CREGS 8
71
72	#define N_X86_DREGS 8
73
74	#define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" }
75	#define N_X86_CONDS 8
76
77	#define X86_MODEL_8086 1
78	#define X86_MODEL_80286 2
79	#define X86_MODEL_80386 3
80	#define X86_MODEL_80486 4
81	#define X86_MODEL_PENTIUM 5
82	#define X86_MODEL_AMD64 6
83
84	struct x86_model {
85	int model_number;
86	char *name;
87	};
88
89	#define x86_models { \
90	{ X86_MODEL_8086, "8086" }, \
91	{ X86_MODEL_80286, "80286" }, \
92	{ X86_MODEL_80386, "80386" }, \
93	{ X86_MODEL_80486, "80486" }, \
94	{ X86_MODEL_PENTIUM, "PENTIUM" }, \
95	{ X86_MODEL_AMD64, "AMD64" }, \
96	{ 0, NULL } \
97	}
98
99	#define X86_N_IC_ARGS 3
100	#define X86_INSTR_ALIGNMENT_SHIFT 0
101	#define X86_IC_ENTRIES_SHIFT 12
102	#define X86_IC_ENTRIES_PER_PAGE (1 << X86_IC_ENTRIES_SHIFT)
103	#define X86_PC_TO_IC_ENTRY(a) ((a) & (X86_IC_ENTRIES_PER_PAGE-1))
104	#define X86_ADDR_TO_PAGENR(a) ((a) >> X86_IC_ENTRIES_SHIFT)
105
106	#define X86_L2N 17
107	#define X86_L3N 18
108
109	DYNTRANS_MISC_DECLARATIONS(x86,X86,uint64_t)
110	DYNTRANS_MISC64_DECLARATIONS(x86,X86,uint8_t)
111
112	#define X86_MAX_VPH_TLB_ENTRIES 128
113
114	struct descriptor_cache {
115	int valid;
116	int default_op_size;
117	int access_rights;
118	int descr_type;
119	int readable;
120	int writable;
121	int granularity;
122	uint64_t base;
123	uint64_t limit;
124	};
125
126
127	struct x86_cpu {
128	struct x86_model model;
129
130	int halted;
131	int interrupt_asserted;
132
133	int cursegment; /* NOTE: 0..N_X86_SEGS-1 */
134	int seg_override; /* 0 or 1 */
135
136	uint64_t tsc; /* time stamp counter */
137
138	uint64_t gdtr; /* global descriptor table */
139	uint32_t gdtr_limit;
140	uint64_t idtr; /* interrupt descriptor table */
141	uint32_t idtr_limit;
142
143	uint16_t tr; /* task register */
144	uint64_t tr_base;
145	uint32_t tr_limit;
146	uint16_t ldtr; /* local descriptor table register */
147	uint64_t ldtr_base;
148	uint32_t ldtr_limit;
149
150	uint64_t rflags;
151	uint64_t cr[N_X86_CREGS]; /* control registers */
152	uint64_t dr[N_X86_DREGS]; /* debug registers */
153
154	uint16_t s[N_X86_SEGS]; /* segment selectors */
155	struct descriptor_cache descr_cache[N_X86_SEGS];
156
157	uint64_t r[N_X86_REGS]; /* GPRs */
158
159	/* FPU: */
160	uint16_t fpu_sw; /* status word */
161	uint16_t fpu_cw; /* control word */
162
163	/* MSRs: */
164	uint64_t efer;
165
166
167	/*
168	* Instruction translation cache and Virtual->Physical->Host
169	* address translation:
170	*/
171	DYNTRANS_ITC(x86)
172	VPH_TLBS(x86,X86)
173	VPH32(x86,X86,uint64_t,uint8_t)
174	VPH64(x86,X86,uint8_t)
175	};
176
177
178	#define X86_FLAGS_CF (1) /* Carry Flag */
179	#define X86_FLAGS_PF (4) /* Parity Flag */
180	#define X86_FLAGS_AF (16) /* Adjust/AuxilaryCarry Flag */
181	#define X86_FLAGS_ZF (64) /* Zero Flag */
182	#define X86_FLAGS_SF (128) /* Sign Flag */
183	#define X86_FLAGS_TF (256) /* Trap Flag */
184	#define X86_FLAGS_IF (512) /* Interrupt Enable Flag */
185	#define X86_FLAGS_DF (1024) /* Direction Flag */
186	#define X86_FLAGS_OF (2048) /* Overflow Flag */
187	/* Bits 12 and 13 are I/O Privilege Level */
188	#define X86_FLAGS_NT (1<<14) /* Nested Task Flag */
189	#define X86_FLAGS_RF (1<<16) /* Resume Flag */
190	#define X86_FLAGS_VM (1<<17) /* VM86 Flag */
191	#define X86_FLAGS_AC (1<<18) /* Alignment Check */
192	#define X86_FLAGS_VIF (1<<19) /* ? */
193	#define X86_FLAGS_VIP (1<<20) /* ? */
194	#define X86_FLAGS_ID (1<<21) /* CPUID present */
195
196	#define X86_CR0_PE 0x00000001 /* Protection Enable */
197	#define X86_CR0_MP 0x00000002
198	#define X86_CR0_EM 0x00000004
199	#define X86_CR0_TS 0x00000008
200	#define X86_CR0_ET 0x00000010
201	#define X86_CR0_NE 0x00000020
202	#define X86_CR0_WP 0x00010000
203	#define X86_CR0_AM 0x00040000
204	#define X86_CR0_NW 0x20000000
205	#define X86_CR0_CD 0x40000000
206	#define X86_CR0_PG 0x80000000 /* Paging Enable */
207
208	#define X86_CR4_OSXMEX 0x00000400
209	#define X86_CR4_OSFXSR 0x00000200
210	#define X86_CR4_PCE 0x00000100
211	#define X86_CR4_PGE 0x00000080
212	#define X86_CR4_MCE 0x00000040
213	#define X86_CR4_PAE 0x00000020
214	#define X86_CR4_PSE 0x00000010
215	#define X86_CR4_DE 0x00000008
216	#define X86_CR4_TSD 0x00000004 /* Time Stamp Disable */
217	#define X86_CR4_PVI 0x00000002
218	#define X86_CR4_VME 0x00000001
219
220	/* EFER bits: */
221	#define X86_EFER_FFXSR 0x00004000
222	#define X86_EFER_LMSLE 0x00002000
223	#define X86_EFER_NXE 0x00000800
224	#define X86_EFER_LMA 0x00000400
225	#define X86_EFER_LME 0x00000100 /* Long Mode (64-bit) */
226	#define X86_EFER_SCE 0x00000001
227
228	/* CPUID feature bits: */
229	#define X86_CPUID_ECX_ETPRD 0x00004000
230	#define X86_CPUID_ECX_CX16 0x00002000 /* cmpxchg16b */
231	#define X86_CPUID_ECX_CID 0x00000400
232	#define X86_CPUID_ECX_TM2 0x00000100
233	#define X86_CPUID_ECX_EST 0x00000080
234	#define X86_CPUID_ECX_DSCPL 0x00000010
235	#define X86_CPUID_ECX_MON 0x00000004
236	#define X86_CPUID_ECX_SSE3 0x00000001
237	#define X86_CPUID_EDX_PBE 0x80000000 /* pending break event */
238	#define X86_CPUID_EDX_IA64 0x40000000
239	#define X86_CPUID_EDX_TM1 0x20000000 /* thermal interrupt */
240	#define X86_CPUID_EDX_HTT 0x10000000 /* hyper threading */
241	#define X86_CPUID_EDX_SS 0x08000000 /* self-snoop */
242	#define X86_CPUID_EDX_SSE2 0x04000000
243	#define X86_CPUID_EDX_SSE 0x02000000
244	#define X86_CPUID_EDX_FXSR 0x01000000
245	#define X86_CPUID_EDX_MMX 0x00800000
246	#define X86_CPUID_EDX_ACPI 0x00400000
247	#define X86_CPUID_EDX_DTES 0x00200000
248	#define X86_CPUID_EDX_CLFL 0x00080000
249	#define X86_CPUID_EDX_PSN 0x00040000
250	#define X86_CPUID_EDX_PSE36 0x00020000
251	#define X86_CPUID_EDX_PAT 0x00010000
252	#define X86_CPUID_EDX_CMOV 0x00008000
253	#define X86_CPUID_EDX_MCA 0x00004000
254	#define X86_CPUID_EDX_PGE 0x00002000 /* global bit in PDE/PTE */
255	#define X86_CPUID_EDX_MTRR 0x00001000
256	#define X86_CPUID_EDX_SEP 0x00000800 /* sysenter/sysexit */
257	#define X86_CPUID_EDX_APIC 0x00000200
258	#define X86_CPUID_EDX_CX8 0x00000100 /* cmpxchg8b */
259	#define X86_CPUID_EDX_MCE 0x00000080
260	#define X86_CPUID_EDX_PAE 0x00000040
261	#define X86_CPUID_EDX_MSR 0x00000020
262	#define X86_CPUID_EDX_TSC 0x00000010
263	#define X86_CPUID_EDX_PSE 0x00000008
264	#define X86_CPUID_EDX_DE 0x00000004
265	#define X86_CPUID_EDX_VME 0x00000002
266	#define X86_CPUID_EDX_FPU 0x00000001
267
268	/* Extended CPUID flags: */
269	#define X86_CPUID_EXT_ECX_CR8D 0x00000010
270	#define X86_CPUID_EXT_ECX_CMP 0x00000002
271	#define X86_CPUID_EXT_ECX_AHF64 0x00000001
272	#define X86_CPUID_EXT_EDX_LM 0x20000000 /* AMD64 Long Mode */
273	#define X86_CPUID_EXT_EDX_FFXSR 0x02000000
274	/* TODO: Many bits are duplicated in the Extended CPUID bits! */
275
276	#define X86_IO_BASE 0x1000000000ULL
277
278	/* Privilege level in the lowest 2 bits of a selector: */
279	#define X86_PL_MASK 0x0003
280	#define X86_RING0 0
281	#define X86_RING1 1
282	#define X86_RING2 2
283	#define X86_RING3 3
284
285	#define DESCR_TYPE_CODE 1
286	#define DESCR_TYPE_DATA 2
287
288
289	#define LONG_MODE (cpu->cd.x86.efer & X86_EFER_LME)
290	#define PROTECTED_MODE (cpu->cd.x86.cr[0] & X86_CR0_PE)
291	#define REAL_MODE (!PROTECTED_MODE)
292
293
294	/* cpu_x86.c: */
295	void reload_segment_descriptor(struct cpu *cpu, int segnr, int selector,
296	uint64_t *curpcp);
297	int x86_interrupt(struct cpu *cpu, int nr, int errcode);
298	int x86_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
299	unsigned char *data, size_t len, int writeflag, int cache_flags);
300	void x86_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
301	unsigned char *host_page, int writeflag, uint64_t paddr_page);
302	void x8632_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
303	unsigned char *host_page, int writeflag, uint64_t paddr_page);
304	void x86_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
305	void x8632_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
306	void x86_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
307	void x8632_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
308	void x86_init_64bit_dummy_tables(struct cpu *cpu);
309	int x86_cpu_family_init(struct cpu_family *);
310
311
312	/* memory_x86.c: */
313	int x86_translate_v2p(struct cpu *cpu, uint64_t vaddr,
314	uint64_t *return_addr, int flags);
315
316	#endif /* CPU_X86_H */