/[gxemul]/trunk/src/include/cpu_x86.h
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Contents of /trunk/src/include/cpu_x86.h

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Revision 6 - (show annotations)
Mon Oct 8 16:18:11 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 8637 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.772 2005/06/04 12:02:16 debug Exp $
20050428	Disabling the "-fmove-all-movables" option in the configure
		script, because it causes the compile to fail on OpenBSD/sgi.
20050502	Minor updates.
20050503	Removing the WRT54G mode (it was bogus anyway), and adding a
		comment about Windows NT for MIPS in doc/experiments.html.
		Minor updates to the x86 instruction decoding.
20050504	Adding some more x86 instructions.
		Adding support for reading files from ISO9660 CDROMs (including
		gzipped files). It's an ugly hack, but it seems to work.
		Various other minor updates (dev_vga.c, pc_bios.c etc).
20050505	Some more x86-related updates.
		Beginning (what I hope will be) a major code cleanup phase.
		"bootris" (an x86 bootsector) runs :-)
20050506	Adding some more x86 instructions.
20050507	tmpnam => mkstemp.
		Working on a hack to allow VGA charcells to be shown even when
		not running with X11.
		Adding more x86 instructions.
20050508	x86 32-bit SIB addressing fix, and more instructions.
20050509	Adding more x86 instructions.
20050510	Minor documentation updates, and other updates (x86 stuff etc.)
20050511	More x86-related updates.
20050513	Various updates, mostly x86-related. (Trying to fix flag 
		calculation, factoring out the ugly shift/rotate code, and
		some other things.)
20050514	Adding support for loading some old i386 a.out executables.
		Finally beginning the cleanup of machine/PROM/bios dependant
		info.
		Some minor documentation updates.
		Trying to clean up ARCBIOS stuff a little.
20050515	Trying to make it possible to actually use more than one disk
		type per machine (floppy, ide, scsi).
		Trying to clean up the kbd vs PROM console stuff. (For PC and
		ARC emulation modes, mostly.)
		Beginning to add an 8259 interrupt controller, and connecting
		it to the x86 emulation.
20050516	The first x86 interrupts seem to work (keyboard stuff).
		Adding a 8253/8254 programmable interval timer skeleton.
		FreeDOS now reaches a command prompt and can be interacted
		with.
20050517	After some bugfixes, MS-DOS also (sometimes) reaches a
		command prompt now.
		Trying to fix the pckbc to work with MS-DOS' keyb.com, but no
		success yet.
20050518	Adding a simple 32-bit x86 MMU skeleton.
20050519	Some more work on the x86 stuff. (Beginning the work on paging,
		and various other fixes).
20050520	More updates. Working on dev_vga (4-bit graphics modes), adding
		40 columns support to the PC bios emulation.
		Trying to add support for resizing windows when switching
		between graphics modes.
20050521	Many more x86-related updates.
20050522	Correcting the initial stack pointer's sign-extension for
		ARCBIOS emulation (thanks to Alec Voropay for noticing the
		error).
		Continuing on the cleanup (ARCBIOS etc).
		dev_vga updates.
20050523	More x86 updates: trying to add some support for protected mode
		interrupts (via gate descriptors) and many other fixes.
		More ARCBIOS cleanup.
		Adding a device flag which indicates that reads cause no
		side-effects. (Useful for the "dump" command in the debugger,
		and other things.)
		Adding support for directly starting up x86 ELFs, skipping the
		bootloader stage. (Most ELFs, however, are not suitable for
		this.)
20050524	Adding simple 32-bit x86 TSS task switching, but no privilege
		level support yet.
		More work on dev_vga. A small "Copper bars" demo works. :-)
		Adding support for Trap Flag (single-step exceptions), at least
		in real mode, and various other x86-related fixes.
20050525	Adding a new disk image prefix (gH;S;) which can be used to
		override the default nr of heads and sectors per track.
20050527	Various bug fixes, more work on the x86 mode (stack change on
		interrupts between different priv.levels), and some minor
		documentation updates.
20050528	Various fixes (x86 stuff).
20050529	More x86 fixes. An OpenBSD/i386 bootfloppy reaches userland
		and can be interacted with (although there are problems with
		key repetition). NetBSD/i386 triggers a serious CISC-related
		problem: instruction fetches across page boundaries, where
		the later part isn't actually part of the instruction.
20050530	Various minor updates. (Documentation updates, etc.)
20050531	Adding some experimental code (experiments/new_test_*) which
		could be useful for dynamic (but not binary) translation in
		the future.
20050602	Adding a dummy ARM skeleton.
		Fixing the pckbc key repetition problem (by adding release
		scancodes for all keypresses).
20050603	Minor updates for the next release.
20050604	Release testing. Minor updates.

==============  RELEASE 0.3.3  ==============

20050604	There'll probably be a 0.3.3.1 release soon, with some very
		very tiny updates.


1 #ifndef CPU_X86_H
2 #define CPU_X86_H
3
4 /*
5 * Copyright (C) 2005 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_x86.h,v 1.31 2005/05/29 19:21:05 debug Exp $
32 */
33
34 #include "misc.h"
35
36
37 struct cpu_family;
38
39 #define N_X86_REGS 16
40
41 #define x86_reg_names { \
42 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \
43 "08", "09", "10", "11", "12", "13", "14", "15" }
44 #define x86_reg_names_bytes { \
45 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" }
46
47 #define X86_R_AX 0
48 #define X86_R_CX 1
49 #define X86_R_DX 2
50 #define X86_R_BX 3
51 #define X86_R_SP 4
52 #define X86_R_BP 5
53 #define X86_R_SI 6
54 #define X86_R_DI 7
55
56 #define N_X86_SEGS 8
57 /* (All of these 8 are not actually used.) */
58
59 #define X86_S_ES 0
60 #define X86_S_CS 1
61 #define X86_S_SS 2
62 #define X86_S_DS 3
63 #define X86_S_FS 4
64 #define X86_S_GS 5
65
66 #define x86_seg_names { "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7" }
67
68 #define N_X86_CREGS 8
69
70 #define N_X86_DREGS 8
71
72 #define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" }
73 #define N_X86_CONDS 8
74
75 #define X86_MODEL_8086 1
76 #define X86_MODEL_80286 2
77 #define X86_MODEL_80386 3
78 #define X86_MODEL_80486 4
79 #define X86_MODEL_PENTIUM 5
80 #define X86_MODEL_AMD64 6
81
82 struct x86_model {
83 int model_number;
84 char *name;
85 };
86
87 #define x86_models { \
88 { X86_MODEL_8086, "8086" }, \
89 { X86_MODEL_80286, "80286" }, \
90 { X86_MODEL_80386, "80386" }, \
91 { X86_MODEL_80486, "80486" }, \
92 { X86_MODEL_PENTIUM, "PENTIUM" }, \
93 { X86_MODEL_AMD64, "AMD64" }, \
94 { 0, NULL } \
95 }
96
97
98 struct descriptor_cache {
99 int valid;
100 int default_op_size;
101 int access_rights;
102 int descr_type;
103 int readable;
104 int writable;
105 int granularity;
106 uint64_t base;
107 uint64_t limit;
108 };
109
110
111 struct x86_cpu {
112 struct x86_model model;
113
114 int halted;
115 int interrupt_asserted;
116
117 int cursegment; /* NOTE: 0..N_X86_SEGS-1 */
118 int seg_override; /* 0 or 1 */
119
120 uint64_t tsc; /* time stamp counter */
121
122 uint64_t gdtr; /* global descriptor table */
123 uint32_t gdtr_limit;
124 uint64_t idtr; /* interrupt descriptor table */
125 uint32_t idtr_limit;
126
127 uint16_t tr; /* task register */
128 uint64_t tr_base;
129 uint32_t tr_limit;
130 uint16_t ldtr; /* local descriptor table register */
131 uint64_t ldtr_base;
132 uint32_t ldtr_limit;
133
134 uint64_t rflags;
135 uint64_t cr[N_X86_CREGS]; /* control registers */
136 uint64_t dr[N_X86_DREGS]; /* debug registers */
137
138 uint16_t s[N_X86_SEGS]; /* segment selectors */
139 struct descriptor_cache descr_cache[N_X86_SEGS];
140
141 uint64_t r[N_X86_REGS]; /* GPRs */
142
143 /* FPU: */
144 uint16_t fpu_sw; /* status word */
145 uint16_t fpu_cw; /* control word */
146
147 /* MSRs: */
148 uint64_t efer;
149 };
150
151
152 #define X86_FLAGS_CF (1) /* Carry Flag */
153 #define X86_FLAGS_PF (4) /* Parity Flag */
154 #define X86_FLAGS_AF (16) /* Adjust/AuxilaryCarry Flag */
155 #define X86_FLAGS_ZF (64) /* Zero Flag */
156 #define X86_FLAGS_SF (128) /* Sign Flag */
157 #define X86_FLAGS_TF (256) /* Trap Flag */
158 #define X86_FLAGS_IF (512) /* Interrupt Enable Flag */
159 #define X86_FLAGS_DF (1024) /* Direction Flag */
160 #define X86_FLAGS_OF (2048) /* Overflow Flag */
161 /* Bits 12 and 13 are I/O Privilege Level */
162 #define X86_FLAGS_NT (1<<14) /* Nested Task Flag */
163 #define X86_FLAGS_RF (1<<16) /* Resume Flag */
164 #define X86_FLAGS_VM (1<<17) /* VM86 Flag */
165 #define X86_FLAGS_AC (1<<18) /* Alignment Check */
166 #define X86_FLAGS_VIF (1<<19) /* ? */
167 #define X86_FLAGS_VIP (1<<20) /* ? */
168 #define X86_FLAGS_ID (1<<21) /* CPUID present */
169
170 #define X86_CR0_PE 0x00000001 /* Protection Enable */
171 #define X86_CR0_MP 0x00000002
172 #define X86_CR0_EM 0x00000004
173 #define X86_CR0_TS 0x00000008
174 #define X86_CR0_ET 0x00000010
175 #define X86_CR0_NE 0x00000020
176 #define X86_CR0_WP 0x00010000
177 #define X86_CR0_AM 0x00040000
178 #define X86_CR0_NW 0x20000000
179 #define X86_CR0_CD 0x40000000
180 #define X86_CR0_PG 0x80000000 /* Paging Enable */
181
182 #define X86_CR4_OSXMEX 0x00000400
183 #define X86_CR4_OSFXSR 0x00000200
184 #define X86_CR4_PCE 0x00000100
185 #define X86_CR4_PGE 0x00000080
186 #define X86_CR4_MCE 0x00000040
187 #define X86_CR4_PAE 0x00000020
188 #define X86_CR4_PSE 0x00000010
189 #define X86_CR4_DE 0x00000008
190 #define X86_CR4_TSD 0x00000004 /* Time Stamp Disable */
191 #define X86_CR4_PVI 0x00000002
192 #define X86_CR4_VME 0x00000001
193
194 /* EFER bits: */
195 #define X86_EFER_FFXSR 0x00004000
196 #define X86_EFER_LMSLE 0x00002000
197 #define X86_EFER_NXE 0x00000800
198 #define X86_EFER_LMA 0x00000400
199 #define X86_EFER_LME 0x00000100 /* Long Mode (64-bit) */
200 #define X86_EFER_SCE 0x00000001
201
202 /* CPUID feature bits: */
203 #define X86_CPUID_ECX_ETPRD 0x00004000
204 #define X86_CPUID_ECX_CX16 0x00002000 /* cmpxchg16b */
205 #define X86_CPUID_ECX_CID 0x00000400
206 #define X86_CPUID_ECX_TM2 0x00000100
207 #define X86_CPUID_ECX_EST 0x00000080
208 #define X86_CPUID_ECX_DSCPL 0x00000010
209 #define X86_CPUID_ECX_MON 0x00000004
210 #define X86_CPUID_ECX_SSE3 0x00000001
211 #define X86_CPUID_EDX_PBE 0x80000000 /* pending break event */
212 #define X86_CPUID_EDX_IA64 0x40000000
213 #define X86_CPUID_EDX_TM1 0x20000000 /* thermal interrupt */
214 #define X86_CPUID_EDX_HTT 0x10000000 /* hyper threading */
215 #define X86_CPUID_EDX_SS 0x08000000 /* self-snoop */
216 #define X86_CPUID_EDX_SSE2 0x04000000
217 #define X86_CPUID_EDX_SSE 0x02000000
218 #define X86_CPUID_EDX_FXSR 0x01000000
219 #define X86_CPUID_EDX_MMX 0x00800000
220 #define X86_CPUID_EDX_ACPI 0x00400000
221 #define X86_CPUID_EDX_DTES 0x00200000
222 #define X86_CPUID_EDX_CLFL 0x00080000
223 #define X86_CPUID_EDX_PSN 0x00040000
224 #define X86_CPUID_EDX_PSE36 0x00020000
225 #define X86_CPUID_EDX_PAT 0x00010000
226 #define X86_CPUID_EDX_CMOV 0x00008000
227 #define X86_CPUID_EDX_MCA 0x00004000
228 #define X86_CPUID_EDX_PGE 0x00002000 /* global bit in PDE/PTE */
229 #define X86_CPUID_EDX_MTRR 0x00001000
230 #define X86_CPUID_EDX_SEP 0x00000800 /* sysenter/sysexit */
231 #define X86_CPUID_EDX_APIC 0x00000200
232 #define X86_CPUID_EDX_CX8 0x00000100 /* cmpxchg8b */
233 #define X86_CPUID_EDX_MCE 0x00000080
234 #define X86_CPUID_EDX_PAE 0x00000040
235 #define X86_CPUID_EDX_MSR 0x00000020
236 #define X86_CPUID_EDX_TSC 0x00000010
237 #define X86_CPUID_EDX_PSE 0x00000008
238 #define X86_CPUID_EDX_DE 0x00000004
239 #define X86_CPUID_EDX_VME 0x00000002
240 #define X86_CPUID_EDX_FPU 0x00000001
241
242 /* Extended CPUID flags: */
243 #define X86_CPUID_EXT_ECX_CR8D 0x00000010
244 #define X86_CPUID_EXT_ECX_CMP 0x00000002
245 #define X86_CPUID_EXT_ECX_AHF64 0x00000001
246 #define X86_CPUID_EXT_EDX_LM 0x20000000 /* AMD64 Long Mode */
247 #define X86_CPUID_EXT_EDX_FFXSR 0x02000000
248 /* TODO: Many bits are duplicated in the Extended CPUID bits! */
249
250 #define X86_IO_BASE 0x1000000000ULL
251
252 /* Privilege level in the lowest 2 bits of a selector: */
253 #define X86_PL_MASK 0x0003
254 #define X86_RING0 0
255 #define X86_RING1 1
256 #define X86_RING2 2
257 #define X86_RING3 3
258
259 #define DESCR_TYPE_CODE 1
260 #define DESCR_TYPE_DATA 2
261
262
263 #define PROTECTED_MODE (cpu->cd.x86.cr[0] & X86_CR0_PE)
264 #define REAL_MODE (!PROTECTED_MODE)
265
266 /* cpu_x86.c: */
267 void reload_segment_descriptor(struct cpu *cpu, int segnr, int selector,
268 uint64_t *curpcp);
269 int x86_interrupt(struct cpu *cpu, int nr, int errcode);
270 int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
271 unsigned char *data, size_t len, int writeflag, int cache_flags);
272 int x86_cpu_family_init(struct cpu_family *);
273
274
275 #endif /* CPU_X86_H */

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