/[gxemul]/trunk/src/include/cpu_x86.h
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Contents of /trunk/src/include/cpu_x86.h

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Revision 12 - (show annotations)
Mon Oct 8 16:18:38 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 10366 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
		shifts).
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		backend.
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		code).
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		functionality).
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
		yet.)
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============
1 #ifndef CPU_X86_H
2 #define CPU_X86_H
3
4 /*
5 * Copyright (C) 2005 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_x86.h,v 1.32 2005/08/14 23:44:23 debug Exp $
32 */
33
34 #include "misc.h"
35
36
37 struct cpu_family;
38
39 #define N_X86_REGS 16
40
41 #define x86_reg_names { \
42 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \
43 "08", "09", "10", "11", "12", "13", "14", "15" }
44 #define x86_reg_names_bytes { \
45 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" }
46
47 #define X86_R_AX 0
48 #define X86_R_CX 1
49 #define X86_R_DX 2
50 #define X86_R_BX 3
51 #define X86_R_SP 4
52 #define X86_R_BP 5
53 #define X86_R_SI 6
54 #define X86_R_DI 7
55
56 #define N_X86_SEGS 8
57 /* (All of these 8 are not actually used.) */
58
59 #define X86_S_ES 0
60 #define X86_S_CS 1
61 #define X86_S_SS 2
62 #define X86_S_DS 3
63 #define X86_S_FS 4
64 #define X86_S_GS 5
65
66 #define x86_seg_names { "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7" }
67
68 #define N_X86_CREGS 8
69
70 #define N_X86_DREGS 8
71
72 #define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" }
73 #define N_X86_CONDS 8
74
75 #define X86_MODEL_8086 1
76 #define X86_MODEL_80286 2
77 #define X86_MODEL_80386 3
78 #define X86_MODEL_80486 4
79 #define X86_MODEL_PENTIUM 5
80 #define X86_MODEL_AMD64 6
81
82 struct x86_model {
83 int model_number;
84 char *name;
85 };
86
87 #define x86_models { \
88 { X86_MODEL_8086, "8086" }, \
89 { X86_MODEL_80286, "80286" }, \
90 { X86_MODEL_80386, "80386" }, \
91 { X86_MODEL_80486, "80486" }, \
92 { X86_MODEL_PENTIUM, "PENTIUM" }, \
93 { X86_MODEL_AMD64, "AMD64" }, \
94 { 0, NULL } \
95 }
96
97 #define X86_N_IC_ARGS 3
98 #define X86_INSTR_ALIGNMENT_SHIFT 0
99 #define X86_IC_ENTRIES_SHIFT 12
100 #define X86_IC_ENTRIES_PER_PAGE (1 << X86_IC_ENTRIES_SHIFT)
101 #define X86_PC_TO_IC_ENTRY(a) ((a) & (X86_IC_ENTRIES_PER_PAGE-1))
102 #define X86_ADDR_TO_PAGENR(a) ((a) >> X86_IC_ENTRIES_SHIFT)
103
104 struct x86_instr_call {
105 void (*f)(struct cpu *, struct x86_instr_call *);
106 size_t arg[X86_N_IC_ARGS];
107 };
108
109 /* Translation cache struct for each physical page: */
110 struct x86_tc_physpage {
111 uint32_t next_ofs; /* or 0 for end of chain */
112 uint64_t physaddr;
113 int flags;
114 struct x86_instr_call ics[X86_IC_ENTRIES_PER_PAGE + 1];
115 };
116
117 #define X86_N_VPH_ENTRIES 1048576
118
119 #define X86_MAX_VPH_TLB_ENTRIES 256
120 struct x86_vpg_tlb_entry {
121 int valid;
122 int writeflag;
123 int64_t timestamp;
124 unsigned char *host_page;
125 uint64_t vaddr_page;
126 uint64_t paddr_page;
127 };
128
129 struct descriptor_cache {
130 int valid;
131 int default_op_size;
132 int access_rights;
133 int descr_type;
134 int readable;
135 int writable;
136 int granularity;
137 uint64_t base;
138 uint64_t limit;
139 };
140
141
142 struct x86_cpu {
143 struct x86_model model;
144
145 int halted;
146 int interrupt_asserted;
147
148 int cursegment; /* NOTE: 0..N_X86_SEGS-1 */
149 int seg_override; /* 0 or 1 */
150
151 uint64_t tsc; /* time stamp counter */
152
153 uint64_t gdtr; /* global descriptor table */
154 uint32_t gdtr_limit;
155 uint64_t idtr; /* interrupt descriptor table */
156 uint32_t idtr_limit;
157
158 uint16_t tr; /* task register */
159 uint64_t tr_base;
160 uint32_t tr_limit;
161 uint16_t ldtr; /* local descriptor table register */
162 uint64_t ldtr_base;
163 uint32_t ldtr_limit;
164
165 uint64_t rflags;
166 uint64_t cr[N_X86_CREGS]; /* control registers */
167 uint64_t dr[N_X86_DREGS]; /* debug registers */
168
169 uint16_t s[N_X86_SEGS]; /* segment selectors */
170 struct descriptor_cache descr_cache[N_X86_SEGS];
171
172 uint64_t r[N_X86_REGS]; /* GPRs */
173
174 /* FPU: */
175 uint16_t fpu_sw; /* status word */
176 uint16_t fpu_cw; /* control word */
177
178 /* MSRs: */
179 uint64_t efer;
180
181
182 /*
183 * Instruction translation cache:
184 */
185
186 /* cur_ic_page is a pointer to an array of X86_IC_ENTRIES_PER_PAGE
187 instruction call entries. next_ic points to the next such
188 call to be executed. */
189 struct x86_tc_physpage *cur_physpage;
190 struct x86_instr_call *cur_ic_page;
191 struct x86_instr_call *next_ic;
192
193
194 /*
195 * Virtual -> physical -> host address translation:
196 *
197 * host_load and host_store point to arrays of X86_N_VPH_ENTRIES
198 * pointers (to host pages); phys_addr points to an array of
199 * X86_N_VPH_ENTRIES uint32_t.
200 */
201
202 struct x86_vpg_tlb_entry vph_tlb_entry[X86_MAX_VPH_TLB_ENTRIES];
203 unsigned char *host_load[X86_N_VPH_ENTRIES];
204 unsigned char *host_store[X86_N_VPH_ENTRIES];
205 uint32_t phys_addr[X86_N_VPH_ENTRIES];
206 struct x86_tc_physpage *phys_page[X86_N_VPH_ENTRIES];
207 };
208
209
210 #define X86_FLAGS_CF (1) /* Carry Flag */
211 #define X86_FLAGS_PF (4) /* Parity Flag */
212 #define X86_FLAGS_AF (16) /* Adjust/AuxilaryCarry Flag */
213 #define X86_FLAGS_ZF (64) /* Zero Flag */
214 #define X86_FLAGS_SF (128) /* Sign Flag */
215 #define X86_FLAGS_TF (256) /* Trap Flag */
216 #define X86_FLAGS_IF (512) /* Interrupt Enable Flag */
217 #define X86_FLAGS_DF (1024) /* Direction Flag */
218 #define X86_FLAGS_OF (2048) /* Overflow Flag */
219 /* Bits 12 and 13 are I/O Privilege Level */
220 #define X86_FLAGS_NT (1<<14) /* Nested Task Flag */
221 #define X86_FLAGS_RF (1<<16) /* Resume Flag */
222 #define X86_FLAGS_VM (1<<17) /* VM86 Flag */
223 #define X86_FLAGS_AC (1<<18) /* Alignment Check */
224 #define X86_FLAGS_VIF (1<<19) /* ? */
225 #define X86_FLAGS_VIP (1<<20) /* ? */
226 #define X86_FLAGS_ID (1<<21) /* CPUID present */
227
228 #define X86_CR0_PE 0x00000001 /* Protection Enable */
229 #define X86_CR0_MP 0x00000002
230 #define X86_CR0_EM 0x00000004
231 #define X86_CR0_TS 0x00000008
232 #define X86_CR0_ET 0x00000010
233 #define X86_CR0_NE 0x00000020
234 #define X86_CR0_WP 0x00010000
235 #define X86_CR0_AM 0x00040000
236 #define X86_CR0_NW 0x20000000
237 #define X86_CR0_CD 0x40000000
238 #define X86_CR0_PG 0x80000000 /* Paging Enable */
239
240 #define X86_CR4_OSXMEX 0x00000400
241 #define X86_CR4_OSFXSR 0x00000200
242 #define X86_CR4_PCE 0x00000100
243 #define X86_CR4_PGE 0x00000080
244 #define X86_CR4_MCE 0x00000040
245 #define X86_CR4_PAE 0x00000020
246 #define X86_CR4_PSE 0x00000010
247 #define X86_CR4_DE 0x00000008
248 #define X86_CR4_TSD 0x00000004 /* Time Stamp Disable */
249 #define X86_CR4_PVI 0x00000002
250 #define X86_CR4_VME 0x00000001
251
252 /* EFER bits: */
253 #define X86_EFER_FFXSR 0x00004000
254 #define X86_EFER_LMSLE 0x00002000
255 #define X86_EFER_NXE 0x00000800
256 #define X86_EFER_LMA 0x00000400
257 #define X86_EFER_LME 0x00000100 /* Long Mode (64-bit) */
258 #define X86_EFER_SCE 0x00000001
259
260 /* CPUID feature bits: */
261 #define X86_CPUID_ECX_ETPRD 0x00004000
262 #define X86_CPUID_ECX_CX16 0x00002000 /* cmpxchg16b */
263 #define X86_CPUID_ECX_CID 0x00000400
264 #define X86_CPUID_ECX_TM2 0x00000100
265 #define X86_CPUID_ECX_EST 0x00000080
266 #define X86_CPUID_ECX_DSCPL 0x00000010
267 #define X86_CPUID_ECX_MON 0x00000004
268 #define X86_CPUID_ECX_SSE3 0x00000001
269 #define X86_CPUID_EDX_PBE 0x80000000 /* pending break event */
270 #define X86_CPUID_EDX_IA64 0x40000000
271 #define X86_CPUID_EDX_TM1 0x20000000 /* thermal interrupt */
272 #define X86_CPUID_EDX_HTT 0x10000000 /* hyper threading */
273 #define X86_CPUID_EDX_SS 0x08000000 /* self-snoop */
274 #define X86_CPUID_EDX_SSE2 0x04000000
275 #define X86_CPUID_EDX_SSE 0x02000000
276 #define X86_CPUID_EDX_FXSR 0x01000000
277 #define X86_CPUID_EDX_MMX 0x00800000
278 #define X86_CPUID_EDX_ACPI 0x00400000
279 #define X86_CPUID_EDX_DTES 0x00200000
280 #define X86_CPUID_EDX_CLFL 0x00080000
281 #define X86_CPUID_EDX_PSN 0x00040000
282 #define X86_CPUID_EDX_PSE36 0x00020000
283 #define X86_CPUID_EDX_PAT 0x00010000
284 #define X86_CPUID_EDX_CMOV 0x00008000
285 #define X86_CPUID_EDX_MCA 0x00004000
286 #define X86_CPUID_EDX_PGE 0x00002000 /* global bit in PDE/PTE */
287 #define X86_CPUID_EDX_MTRR 0x00001000
288 #define X86_CPUID_EDX_SEP 0x00000800 /* sysenter/sysexit */
289 #define X86_CPUID_EDX_APIC 0x00000200
290 #define X86_CPUID_EDX_CX8 0x00000100 /* cmpxchg8b */
291 #define X86_CPUID_EDX_MCE 0x00000080
292 #define X86_CPUID_EDX_PAE 0x00000040
293 #define X86_CPUID_EDX_MSR 0x00000020
294 #define X86_CPUID_EDX_TSC 0x00000010
295 #define X86_CPUID_EDX_PSE 0x00000008
296 #define X86_CPUID_EDX_DE 0x00000004
297 #define X86_CPUID_EDX_VME 0x00000002
298 #define X86_CPUID_EDX_FPU 0x00000001
299
300 /* Extended CPUID flags: */
301 #define X86_CPUID_EXT_ECX_CR8D 0x00000010
302 #define X86_CPUID_EXT_ECX_CMP 0x00000002
303 #define X86_CPUID_EXT_ECX_AHF64 0x00000001
304 #define X86_CPUID_EXT_EDX_LM 0x20000000 /* AMD64 Long Mode */
305 #define X86_CPUID_EXT_EDX_FFXSR 0x02000000
306 /* TODO: Many bits are duplicated in the Extended CPUID bits! */
307
308 #define X86_IO_BASE 0x1000000000ULL
309
310 /* Privilege level in the lowest 2 bits of a selector: */
311 #define X86_PL_MASK 0x0003
312 #define X86_RING0 0
313 #define X86_RING1 1
314 #define X86_RING2 2
315 #define X86_RING3 3
316
317 #define DESCR_TYPE_CODE 1
318 #define DESCR_TYPE_DATA 2
319
320
321 #define PROTECTED_MODE (cpu->cd.x86.cr[0] & X86_CR0_PE)
322 #define REAL_MODE (!PROTECTED_MODE)
323
324 /* cpu_x86.c: */
325 void reload_segment_descriptor(struct cpu *cpu, int segnr, int selector,
326 uint64_t *curpcp);
327 int x86_interrupt(struct cpu *cpu, int nr, int errcode);
328 int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
329 unsigned char *data, size_t len, int writeflag, int cache_flags);
330 int x86_cpu_family_init(struct cpu_family *);
331
332
333 #endif /* CPU_X86_H */
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