/[gxemul]/trunk/src/include/cpu_x86.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Diff of /trunk/src/include/cpu_x86.h

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 6 by dpavlin, Mon Oct 8 16:18:11 2007 UTC revision 12 by dpavlin, Mon Oct 8 16:18:38 2007 UTC
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_x86.h,v 1.31 2005/05/29 19:21:05 debug Exp $   *  $Id: cpu_x86.h,v 1.32 2005/08/14 23:44:23 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 94  struct x86_model { Line 94  struct x86_model {
94          { 0, NULL }                                                     \          { 0, NULL }                                                     \
95          }          }
96    
97    #define X86_N_IC_ARGS                   3
98    #define X86_INSTR_ALIGNMENT_SHIFT       0
99    #define X86_IC_ENTRIES_SHIFT            12
100    #define X86_IC_ENTRIES_PER_PAGE         (1 << X86_IC_ENTRIES_SHIFT)
101    #define X86_PC_TO_IC_ENTRY(a)           ((a) & (X86_IC_ENTRIES_PER_PAGE-1))
102    #define X86_ADDR_TO_PAGENR(a)           ((a) >> X86_IC_ENTRIES_SHIFT)
103    
104    struct x86_instr_call {
105            void    (*f)(struct cpu *, struct x86_instr_call *);
106            size_t  arg[X86_N_IC_ARGS];
107    };
108    
109    /*  Translation cache struct for each physical page:  */
110    struct x86_tc_physpage {
111            uint32_t        next_ofs;       /*  or 0 for end of chain  */
112            uint64_t        physaddr;
113            int             flags;
114            struct x86_instr_call ics[X86_IC_ENTRIES_PER_PAGE + 1];
115    };
116    
117    #define X86_N_VPH_ENTRIES               1048576
118    
119    #define X86_MAX_VPH_TLB_ENTRIES         256
120    struct x86_vpg_tlb_entry {
121            int             valid;
122            int             writeflag;
123            int64_t         timestamp;
124            unsigned char   *host_page;
125            uint64_t        vaddr_page;
126            uint64_t        paddr_page;
127    };
128    
129  struct descriptor_cache {  struct descriptor_cache {
130          int             valid;          int             valid;
# Line 146  struct x86_cpu { Line 177  struct x86_cpu {
177    
178          /*  MSRs:  */          /*  MSRs:  */
179          uint64_t        efer;          uint64_t        efer;
180    
181    
182            /*
183             *  Instruction translation cache:
184             */
185    
186            /*  cur_ic_page is a pointer to an array of X86_IC_ENTRIES_PER_PAGE
187                instruction call entries. next_ic points to the next such
188                call to be executed.  */
189            struct x86_tc_physpage  *cur_physpage;
190            struct x86_instr_call   *cur_ic_page;
191            struct x86_instr_call   *next_ic;
192    
193    
194            /*
195             *  Virtual -> physical -> host address translation:
196             *
197             *  host_load and host_store point to arrays of X86_N_VPH_ENTRIES
198             *  pointers (to host pages); phys_addr points to an array of
199             *  X86_N_VPH_ENTRIES uint32_t.
200             */
201    
202            struct x86_vpg_tlb_entry        vph_tlb_entry[X86_MAX_VPH_TLB_ENTRIES];
203            unsigned char                   *host_load[X86_N_VPH_ENTRIES];
204            unsigned char                   *host_store[X86_N_VPH_ENTRIES];
205            uint32_t                        phys_addr[X86_N_VPH_ENTRIES];
206            struct x86_tc_physpage          *phys_page[X86_N_VPH_ENTRIES];
207  };  };
208    
209    
Legend:
Removed from v.6  
changed lines
  Added in v.12
  ViewVC Help
Powered by ViewVC 1.1.26