--- trunk/src/include/cpu_x86.h 2007/10/08 16:18:06 5 +++ trunk/src/include/cpu_x86.h 2007/10/08 16:18:11 6 @@ -28,7 +28,7 @@ * SUCH DAMAGE. * * - * $Id: cpu_x86.h,v 1.7 2005/04/20 02:05:57 debug Exp $ + * $Id: cpu_x86.h,v 1.31 2005/05/29 19:21:05 debug Exp $ */ #include "misc.h" @@ -41,6 +41,8 @@ #define x86_reg_names { \ "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \ "08", "09", "10", "11", "12", "13", "14", "15" } +#define x86_reg_names_bytes { \ + "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" } #define X86_R_AX 0 #define X86_R_CX 1 @@ -61,17 +63,21 @@ #define X86_S_FS 4 #define X86_S_GS 5 -#define x86_seg_names { "es", "cs", "ss", "ds", "es", "gs", "xx6", "xx7" } +#define x86_seg_names { "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7" } #define N_X86_CREGS 8 +#define N_X86_DREGS 8 + #define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" } #define N_X86_CONDS 8 #define X86_MODEL_8086 1 -#define X86_MODEL_80386 2 -#define X86_MODEL_PENTIUM 3 -#define X86_MODEL_AMD64 4 +#define X86_MODEL_80286 2 +#define X86_MODEL_80386 3 +#define X86_MODEL_80486 4 +#define X86_MODEL_PENTIUM 5 +#define X86_MODEL_AMD64 6 struct x86_model { int model_number; @@ -80,26 +86,66 @@ #define x86_models { \ { X86_MODEL_8086, "8086" }, \ + { X86_MODEL_80286, "80286" }, \ { X86_MODEL_80386, "80386" }, \ + { X86_MODEL_80486, "80486" }, \ { X86_MODEL_PENTIUM, "PENTIUM" }, \ { X86_MODEL_AMD64, "AMD64" }, \ { 0, NULL } \ } +struct descriptor_cache { + int valid; + int default_op_size; + int access_rights; + int descr_type; + int readable; + int writable; + int granularity; + uint64_t base; + uint64_t limit; +}; + + struct x86_cpu { struct x86_model model; - int bits; /* 16, 32, or 64 */ - int mode; /* 16, 32, or 64 */ + int halted; + int interrupt_asserted; + + int cursegment; /* NOTE: 0..N_X86_SEGS-1 */ + int seg_override; /* 0 or 1 */ + + uint64_t tsc; /* time stamp counter */ - uint16_t cursegment; /* for 16-bit memory_rw */ + uint64_t gdtr; /* global descriptor table */ + uint32_t gdtr_limit; + uint64_t idtr; /* interrupt descriptor table */ + uint32_t idtr_limit; + + uint16_t tr; /* task register */ + uint64_t tr_base; + uint32_t tr_limit; + uint16_t ldtr; /* local descriptor table register */ + uint64_t ldtr_base; + uint32_t ldtr_limit; uint64_t rflags; - uint64_t cr[N_X86_CREGS]; + uint64_t cr[N_X86_CREGS]; /* control registers */ + uint64_t dr[N_X86_DREGS]; /* debug registers */ - uint16_t s[N_X86_SEGS]; - uint64_t r[N_X86_REGS]; + uint16_t s[N_X86_SEGS]; /* segment selectors */ + struct descriptor_cache descr_cache[N_X86_SEGS]; + + uint64_t r[N_X86_REGS]; /* GPRs */ + + /* FPU: */ + uint16_t fpu_sw; /* status word */ + uint16_t fpu_cw; /* control word */ + + /* MSRs: */ + uint64_t efer; }; @@ -116,9 +162,111 @@ #define X86_FLAGS_NT (1<<14) /* Nested Task Flag */ #define X86_FLAGS_RF (1<<16) /* Resume Flag */ #define X86_FLAGS_VM (1<<17) /* VM86 Flag */ +#define X86_FLAGS_AC (1<<18) /* Alignment Check */ +#define X86_FLAGS_VIF (1<<19) /* ? */ +#define X86_FLAGS_VIP (1<<20) /* ? */ +#define X86_FLAGS_ID (1<<21) /* CPUID present */ + +#define X86_CR0_PE 0x00000001 /* Protection Enable */ +#define X86_CR0_MP 0x00000002 +#define X86_CR0_EM 0x00000004 +#define X86_CR0_TS 0x00000008 +#define X86_CR0_ET 0x00000010 +#define X86_CR0_NE 0x00000020 +#define X86_CR0_WP 0x00010000 +#define X86_CR0_AM 0x00040000 +#define X86_CR0_NW 0x20000000 +#define X86_CR0_CD 0x40000000 +#define X86_CR0_PG 0x80000000 /* Paging Enable */ + +#define X86_CR4_OSXMEX 0x00000400 +#define X86_CR4_OSFXSR 0x00000200 +#define X86_CR4_PCE 0x00000100 +#define X86_CR4_PGE 0x00000080 +#define X86_CR4_MCE 0x00000040 +#define X86_CR4_PAE 0x00000020 +#define X86_CR4_PSE 0x00000010 +#define X86_CR4_DE 0x00000008 +#define X86_CR4_TSD 0x00000004 /* Time Stamp Disable */ +#define X86_CR4_PVI 0x00000002 +#define X86_CR4_VME 0x00000001 + +/* EFER bits: */ +#define X86_EFER_FFXSR 0x00004000 +#define X86_EFER_LMSLE 0x00002000 +#define X86_EFER_NXE 0x00000800 +#define X86_EFER_LMA 0x00000400 +#define X86_EFER_LME 0x00000100 /* Long Mode (64-bit) */ +#define X86_EFER_SCE 0x00000001 + +/* CPUID feature bits: */ +#define X86_CPUID_ECX_ETPRD 0x00004000 +#define X86_CPUID_ECX_CX16 0x00002000 /* cmpxchg16b */ +#define X86_CPUID_ECX_CID 0x00000400 +#define X86_CPUID_ECX_TM2 0x00000100 +#define X86_CPUID_ECX_EST 0x00000080 +#define X86_CPUID_ECX_DSCPL 0x00000010 +#define X86_CPUID_ECX_MON 0x00000004 +#define X86_CPUID_ECX_SSE3 0x00000001 +#define X86_CPUID_EDX_PBE 0x80000000 /* pending break event */ +#define X86_CPUID_EDX_IA64 0x40000000 +#define X86_CPUID_EDX_TM1 0x20000000 /* thermal interrupt */ +#define X86_CPUID_EDX_HTT 0x10000000 /* hyper threading */ +#define X86_CPUID_EDX_SS 0x08000000 /* self-snoop */ +#define X86_CPUID_EDX_SSE2 0x04000000 +#define X86_CPUID_EDX_SSE 0x02000000 +#define X86_CPUID_EDX_FXSR 0x01000000 +#define X86_CPUID_EDX_MMX 0x00800000 +#define X86_CPUID_EDX_ACPI 0x00400000 +#define X86_CPUID_EDX_DTES 0x00200000 +#define X86_CPUID_EDX_CLFL 0x00080000 +#define X86_CPUID_EDX_PSN 0x00040000 +#define X86_CPUID_EDX_PSE36 0x00020000 +#define X86_CPUID_EDX_PAT 0x00010000 +#define X86_CPUID_EDX_CMOV 0x00008000 +#define X86_CPUID_EDX_MCA 0x00004000 +#define X86_CPUID_EDX_PGE 0x00002000 /* global bit in PDE/PTE */ +#define X86_CPUID_EDX_MTRR 0x00001000 +#define X86_CPUID_EDX_SEP 0x00000800 /* sysenter/sysexit */ +#define X86_CPUID_EDX_APIC 0x00000200 +#define X86_CPUID_EDX_CX8 0x00000100 /* cmpxchg8b */ +#define X86_CPUID_EDX_MCE 0x00000080 +#define X86_CPUID_EDX_PAE 0x00000040 +#define X86_CPUID_EDX_MSR 0x00000020 +#define X86_CPUID_EDX_TSC 0x00000010 +#define X86_CPUID_EDX_PSE 0x00000008 +#define X86_CPUID_EDX_DE 0x00000004 +#define X86_CPUID_EDX_VME 0x00000002 +#define X86_CPUID_EDX_FPU 0x00000001 + +/* Extended CPUID flags: */ +#define X86_CPUID_EXT_ECX_CR8D 0x00000010 +#define X86_CPUID_EXT_ECX_CMP 0x00000002 +#define X86_CPUID_EXT_ECX_AHF64 0x00000001 +#define X86_CPUID_EXT_EDX_LM 0x20000000 /* AMD64 Long Mode */ +#define X86_CPUID_EXT_EDX_FFXSR 0x02000000 +/* TODO: Many bits are duplicated in the Extended CPUID bits! */ + +#define X86_IO_BASE 0x1000000000ULL + +/* Privilege level in the lowest 2 bits of a selector: */ +#define X86_PL_MASK 0x0003 +#define X86_RING0 0 +#define X86_RING1 1 +#define X86_RING2 2 +#define X86_RING3 3 + +#define DESCR_TYPE_CODE 1 +#define DESCR_TYPE_DATA 2 + +#define PROTECTED_MODE (cpu->cd.x86.cr[0] & X86_CR0_PE) +#define REAL_MODE (!PROTECTED_MODE) /* cpu_x86.c: */ +void reload_segment_descriptor(struct cpu *cpu, int segnr, int selector, + uint64_t *curpcp); +int x86_interrupt(struct cpu *cpu, int nr, int errcode); int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags); int x86_cpu_family_init(struct cpu_family *);