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#ifndef CPU_X86_H |
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#define CPU_X86_H |
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|
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_x86.h,v 1.7 2005/04/20 02:05:57 debug Exp $ |
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*/ |
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|
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#include "misc.h" |
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|
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|
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struct cpu_family; |
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|
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#define N_X86_REGS 16 |
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|
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#define x86_reg_names { \ |
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"ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \ |
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"08", "09", "10", "11", "12", "13", "14", "15" } |
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|
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#define X86_R_AX 0 |
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#define X86_R_CX 1 |
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#define X86_R_DX 2 |
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#define X86_R_BX 3 |
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#define X86_R_SP 4 |
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#define X86_R_BP 5 |
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#define X86_R_SI 6 |
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#define X86_R_DI 7 |
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|
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#define N_X86_SEGS 8 |
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/* (All of these 8 are not actually used.) */ |
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|
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#define X86_S_ES 0 |
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#define X86_S_CS 1 |
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#define X86_S_SS 2 |
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#define X86_S_DS 3 |
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#define X86_S_FS 4 |
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#define X86_S_GS 5 |
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|
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#define x86_seg_names { "es", "cs", "ss", "ds", "es", "gs", "xx6", "xx7" } |
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|
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#define N_X86_CREGS 8 |
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|
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#define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" } |
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#define N_X86_CONDS 8 |
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|
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#define X86_MODEL_8086 1 |
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#define X86_MODEL_80386 2 |
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#define X86_MODEL_PENTIUM 3 |
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#define X86_MODEL_AMD64 4 |
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|
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struct x86_model { |
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int model_number; |
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char *name; |
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}; |
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|
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#define x86_models { \ |
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{ X86_MODEL_8086, "8086" }, \ |
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{ X86_MODEL_80386, "80386" }, \ |
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{ X86_MODEL_PENTIUM, "PENTIUM" }, \ |
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{ X86_MODEL_AMD64, "AMD64" }, \ |
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{ 0, NULL } \ |
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} |
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|
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|
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struct x86_cpu { |
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struct x86_model model; |
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|
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int bits; /* 16, 32, or 64 */ |
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int mode; /* 16, 32, or 64 */ |
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|
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uint16_t cursegment; /* for 16-bit memory_rw */ |
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|
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uint64_t rflags; |
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uint64_t cr[N_X86_CREGS]; |
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|
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uint16_t s[N_X86_SEGS]; |
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uint64_t r[N_X86_REGS]; |
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}; |
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|
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|
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#define X86_FLAGS_CF (1) /* Carry Flag */ |
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#define X86_FLAGS_PF (4) /* Parity Flag */ |
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#define X86_FLAGS_AF (16) /* Adjust/AuxilaryCarry Flag */ |
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#define X86_FLAGS_ZF (64) /* Zero Flag */ |
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#define X86_FLAGS_SF (128) /* Sign Flag */ |
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#define X86_FLAGS_TF (256) /* Trap Flag */ |
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#define X86_FLAGS_IF (512) /* Interrupt Enable Flag */ |
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#define X86_FLAGS_DF (1024) /* Direction Flag */ |
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#define X86_FLAGS_OF (2048) /* Overflow Flag */ |
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/* Bits 12 and 13 are I/O Privilege Level */ |
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#define X86_FLAGS_NT (1<<14) /* Nested Task Flag */ |
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#define X86_FLAGS_RF (1<<16) /* Resume Flag */ |
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#define X86_FLAGS_VM (1<<17) /* VM86 Flag */ |
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|
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|
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/* cpu_x86.c: */ |
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int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int x86_cpu_family_init(struct cpu_family *); |
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|
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|
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#endif /* CPU_X86_H */ |