/[gxemul]/trunk/src/include/cpu_x86.h
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Contents of /trunk/src/include/cpu_x86.h

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Revision 4 - (show annotations)
Mon Oct 8 16:18:00 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 3879 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============


1 #ifndef CPU_X86_H
2 #define CPU_X86_H
3
4 /*
5 * Copyright (C) 2005 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_x86.h,v 1.7 2005/04/20 02:05:57 debug Exp $
32 */
33
34 #include "misc.h"
35
36
37 struct cpu_family;
38
39 #define N_X86_REGS 16
40
41 #define x86_reg_names { \
42 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \
43 "08", "09", "10", "11", "12", "13", "14", "15" }
44
45 #define X86_R_AX 0
46 #define X86_R_CX 1
47 #define X86_R_DX 2
48 #define X86_R_BX 3
49 #define X86_R_SP 4
50 #define X86_R_BP 5
51 #define X86_R_SI 6
52 #define X86_R_DI 7
53
54 #define N_X86_SEGS 8
55 /* (All of these 8 are not actually used.) */
56
57 #define X86_S_ES 0
58 #define X86_S_CS 1
59 #define X86_S_SS 2
60 #define X86_S_DS 3
61 #define X86_S_FS 4
62 #define X86_S_GS 5
63
64 #define x86_seg_names { "es", "cs", "ss", "ds", "es", "gs", "xx6", "xx7" }
65
66 #define N_X86_CREGS 8
67
68 #define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" }
69 #define N_X86_CONDS 8
70
71 #define X86_MODEL_8086 1
72 #define X86_MODEL_80386 2
73 #define X86_MODEL_PENTIUM 3
74 #define X86_MODEL_AMD64 4
75
76 struct x86_model {
77 int model_number;
78 char *name;
79 };
80
81 #define x86_models { \
82 { X86_MODEL_8086, "8086" }, \
83 { X86_MODEL_80386, "80386" }, \
84 { X86_MODEL_PENTIUM, "PENTIUM" }, \
85 { X86_MODEL_AMD64, "AMD64" }, \
86 { 0, NULL } \
87 }
88
89
90 struct x86_cpu {
91 struct x86_model model;
92
93 int bits; /* 16, 32, or 64 */
94 int mode; /* 16, 32, or 64 */
95
96 uint16_t cursegment; /* for 16-bit memory_rw */
97
98 uint64_t rflags;
99 uint64_t cr[N_X86_CREGS];
100
101 uint16_t s[N_X86_SEGS];
102 uint64_t r[N_X86_REGS];
103 };
104
105
106 #define X86_FLAGS_CF (1) /* Carry Flag */
107 #define X86_FLAGS_PF (4) /* Parity Flag */
108 #define X86_FLAGS_AF (16) /* Adjust/AuxilaryCarry Flag */
109 #define X86_FLAGS_ZF (64) /* Zero Flag */
110 #define X86_FLAGS_SF (128) /* Sign Flag */
111 #define X86_FLAGS_TF (256) /* Trap Flag */
112 #define X86_FLAGS_IF (512) /* Interrupt Enable Flag */
113 #define X86_FLAGS_DF (1024) /* Direction Flag */
114 #define X86_FLAGS_OF (2048) /* Overflow Flag */
115 /* Bits 12 and 13 are I/O Privilege Level */
116 #define X86_FLAGS_NT (1<<14) /* Nested Task Flag */
117 #define X86_FLAGS_RF (1<<16) /* Resume Flag */
118 #define X86_FLAGS_VM (1<<17) /* VM86 Flag */
119
120
121 /* cpu_x86.c: */
122 int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
123 unsigned char *data, size_t len, int writeflag, int cache_flags);
124 int x86_cpu_family_init(struct cpu_family *);
125
126
127 #endif /* CPU_X86_H */

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