Parent Directory | Revision Log
++ trunk/HISTORY (local) $Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $ 20060219 Various minor updates. Removing the old MIPS16 skeleton code, because it will need to be rewritten for dyntrans anyway. 20060220-22 Removing the non-working dyntrans backend support. Continuing on the 64-bit dyntrans virtual memory generalization. 20060223 More work on the 64-bit vm generalization. 20060225 Beginning on MIPS dyntrans load/store instructions. Minor PPC updates (64-bit load/store, etc). Fixes for the variable-instruction-length framework, some minor AVR updates (a simple Hello World program works!). Beginning on a skeleton for automatically generating documen- tation (for devices etc.). 20060226 PPC updates (adding some more 64-bit instructions, etc). AVR updates (more instructions). FINALLY found and fixed the zs bug, making NetBSD/macppc accept the serial console. 20060301 Adding more AVR instructions. 20060304 Continuing on AVR-related stuff. Beginning on a framework for cycle-accurate device emulation. Adding an experimental "PAL TV" device (just a dummy so far). 20060305 Adding more AVR instructions. Adding a dummy epcom serial controller (for TS7200 emulation). 20060310 Removing the emul() command from configuration files, so only net() and machine() are supported. Minor progress on the MIPS dyntrans rewrite. 20060311 Continuing on the MIPS dyntrans rewrite (adding more instructions, etc). 20060315 Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l], beql, bnel, slti[u], various loads and stores). 20060316 Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely used. Adding more MIPS dyntrans instructions, and fixing bugs. 20060318 Implementing fast loads/stores for MIPS dyntrans (big/little endian, 32-bit and 64-bit modes). 20060320 Making MIPS dyntrans the default configure option; use "--enable-oldmips" to use the old bintrans system. Adding MIPS dyntrans dmult[u]; minor updates. 20060322 Continuing... adding some more instructions. Adding a simple skeleton for demangling C++ "_ZN" symbols. 20060323 Moving src/debugger.c into a new directory (src/debugger/). 20060324 Fixing the hack used to load PPC ELFs (useful for relocated Linux/ppc kernels), and adding a dummy G3 machine mode. 20060325-26 Beginning to experiment with GDB remote serial protocol connections; adding a -G command line option for selecting which TCP port to listen to. 20060330 Beginning a major cleanup to replace things like "0x%016llx" with more correct "0x%016"PRIx64, etc. Continuing on the GDB remote serial protocol support. 20060331 More cleanup, and some minor GDB remote progress. 20060402 Adding a hack to the configure script, to allow compilation on systems that lack PRIx64 etc. 20060406 Removing the temporary FreeBSD/arm hack in dev_ns16550.c and replacing it with a better fix from Olivier Houchard. 20060407 A remote debugger (gdb or ddd) can now start and stop the emulator using the GDB remote serial protocol, and registers and memory can be read. MIPS only for now. 20060408 More GDB progress: single-stepping also works, and also adding support for ARM, PowerPC, and Alpha targets. Continuing on the delay-slot-across-page-boundary issue. 20060412 Minor update: beginning to add support for the SPARC target to the remote GDB functionality. 20060414 Various MIPS updates: adding more instructions for dyntrans (eret, add), and making some exceptions work. Fixing a bug in dmult[u]. Implementing the first SPARC instructions (sethi, or). 20060415 Adding "magic trap" instructions so that PROM calls can be software emulated in MIPS dyntrans. Adding more MIPS dyntrans instructions (ddiv, dadd) and fixing another bug in dmult. 20060416 More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv, rfi, an ugly hack for supporting R2000/R3000 style faked caches, preliminary interrupt support, and various other updates and bugfixes. 20060417 Adding more SPARC instructions (add, sub, sll[x], sra[x], srl[x]), and useful SPARC header definitions. Adding the first (trivial) x86/AMD64 dyntrans instructions (nop, cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other x86 updates related to variable instruction length stuff. Adding unaligned loads/stores to the MIPS dyntrans mode (but still using the pre-dyntrans (slow) imlementation). 20060419 Fixing a MIPS dyntrans exception-in-delay-slot bug. Removing the old "show opcode statistics" functionality, since it wasn't really useful and isn't implemented for dyntrans. Single-stepping (or running with instruction trace) now looks ok with dyntrans with delay-slot architectures. 20060420 Minor hacks (removing the -B command line option when compiled for non-bintrans, and some other very minor updates). Adding (slow) MIPS dyntrans load-linked/store-conditional. 20060422 Applying fixes for bugs discovered by Nils Weller's nwcc (static DEC memmap => now per machine, and adding an extern keyword in cpu_arm_instr.c). Finally found one of the MIPS dyntrans bugs that I've been looking for (copy/paste spelling error BIG vs LITTLE endian in cpu_mips_instr_loadstore.c for 16-bit fast stores). FINALLY found the major MIPS dyntrans bug: slti vs sltiu signed/unsigned code in cpu_mips_instr.c. :-) Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l], ctc1, tlt[u], tge[u], tne, beginning on rdhwr). NetBSD/hpcmips can now reach userland when using dyntrans :-) Adding some more x86 dyntrans instructions. Finally removed the old Alpha-specific virtual memory code, and replaced it with the generic 64-bit version. Beginning to add disassembly support for SPECIAL3 MIPS opcodes. 20060423 Continuing on the delay-slot-across-page-boundary issue; adding an end_of_page2 ic slot (like I had planned before, but had removed for some reason). Adding a quick-and-dirty fallback to legacy coprocessor 1 code (i.e. skipping dyntrans implementation for now). NetBSD/hpcmips and NetBSD/pmax (when running on an emulated R4400) can now be installed and run. :-) (Many bugs left to fix, though.) Adding more MIPS dyntrans instructions: madd[u], msub[u]. Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode maps somewhat (disassembly and dyntrans instruction decoding). 20060424 Adding an isa_revision field to mips_cpu_types.h, and making sure that SPECIAL3 opcodes cause Reserved Instruction exceptions on MIPS32/64 revisions lower than 2. Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor' instructions. 20060425 Removing the -m command line option ("run at most x instructions") and -T ("single_step_on_bad_addr"), because they never worked correctly with dyntrans anyway. Freshening up the man page. 20060428 Adding more MIPS dyntrans instructions: bltzal[l], idle. Enabling MIPS dyntrans compare interrupts. 20060429 FINALLY found the weird dyntrans bug, causing NetBSD etc. to behave strangely: some floating point code (conditional coprocessor branches) could not be reused from the old non-dyntrans code. The "quick-and-dirty fallback" only appeared to work. Fixing by implementing bc1* for MIPS dyntrans. More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0. Freshening up MIPS floating point disassembly appearance. 20060430 Continuing on C790/R5900/TX79 disassembly; implementing 128-bit "por" and "pextlw". 20060504 Disabling -u (userland emulation) unless compiled as unstable development version. Beginning on freshening up the testmachine include files, to make it easier to reuse those files (placing them in src/include/testmachine/), and beginning on a set of "demos" or "tutorials" for the testmachine functionality. Minor updates to the MIPS GDB remote protocol stub. Refreshing doc/experiments.html and gdb_remote.html. Enabling Alpha emulation in the stable release configuration, even though no guest OSes for Alpha can run yet. 20060505 Adding a generic 'settings' object, which will contain references to settable variables (which will later be possible to access using the debugger). 20060506 Updating dev_disk and corresponding demo/documentation (and switching from SCSI to IDE disk types, so it actually works with current test machines :-). 20060510 Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts, so that fseeko() doesn't give a warning. Updating the section about how dyntrans works (the "runnable IR") in doc/intro.html. Instruction updates (some x64=1 checks, some more R5900 dyntrans stuff: better mul/mult separation from MIPS32/64, adding ei and di). Updating MIPS cpuregs.h to a newer one (from NetBSD). Adding more MIPS dyntrans instructions: deret, ehb. 20060514 Adding disassembly and beginning implementation of SPARC wr and wrpr instructions. 20060515 Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1 machines. Adding the 32-bit "rd psr" instruction. 20060517 Disassembly support for the general SPARC rd instruction. Partial implementation of the cmp (subcc) instruction. Some other minor updates (making sure that R5900 processors start up with the EIE bit enabled, otherwise Linux/playstation2 receives no interrupts). 20060519 Minor MIPS updates/cleanups. 20060521 Moving the MeshCube machine into evbmips; this seems to work reasonably well with a snapshot of a NetBSD MeshCube kernel. Cleanup/fix of MIPS config0 register initialization. 20060529 Minor MIPS fixes, including a sign-extension fix to the unaligned load/store code, which makes NetBSD/pmax on R3000 work better with dyntrans. (Ultrix and Linux/DECstation still don't work, though.) 20060530 Minor updates to the Alpha machine mode: adding an AlphaBook mode, an LCA bus (forwarding accesses to an ISA bus), etc. 20060531 Applying a bugfix for the MIPS dyntrans sc[d] instruction from Ondrej Palkovsky. (Many thanks.) 20060601 Minifix to allow ARM immediate msr instruction to not give an error for some valid values. More Alpha updates. 20060602 Some minor Alpha updates. 20060603 Adding the Alpha cmpbge instruction. NetBSD/alpha prints its first boot messages :-) on an emulated Alphabook 1. 20060612 Minor updates; adding a dev_ether.h include file for the testmachine ether device. Continuing the hunt for the dyntrans bug which makes Linux and Ultrix on DECstation behave strangely... FINALLY found it! It seems to be related to invalidation of the translation cache, on tlbw{r,i}. There also seems to be some remaining interrupt-related problems. 20060614 Correcting the implementation of ldc1/sdc1 for MIPS dyntrans (so that it uses 16 32-bit registers if the FR bit in the status register is not set). 20060616 REMOVING BINTRANS COMPLETELY! Removing the old MIPS interpretation mode. Removing the MFHILO_DELAY and instruction delay stuff, because they wouldn't work with dyntrans anyway. 20060617 Some documentation updates (adding "NetBSD-archive" to some URLs, and new Debian/DECstation installation screenshots). Removing the "tracenull" and "enable-caches" configure options. Improving MIPS dyntrans performance somewhat (only invalidate translations if necessary, on writes to the entryhi register, instead of doing it for all cop0 writes). 20060618 More cleanup after the removal of the old MIPS emulation. Trying to fix the MIPS dyntrans performance bugs/bottlenecks; only semi-successful so far (for R3000). 20060620 Minor update to allow clean compilation again on Tru64/Alpha. 20060622 MIPS cleanup and fixes (removing the pc_last stuff, which doesn't make sense with dyntrans anyway, and fixing a cross- page-delay-slot-with-exception case in end_of_page). Removing the old max_random_cycles_per_chunk stuff, and the concept of cycles vs instructions for MIPS emulation. FINALLY found and fixed the bug which caused NetBSD/pmax clocks to behave strangely (it was a load to the zero register, which was treated as a NOP; now it is treated as a load to a dummy scratch register). 20060623 Increasing the dyntrans chunk size back to N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2. Preparing for a quick release, even though there are known bugs, and performance for non-R3000 MIPS emulation is very poor. :-/ Reverting to half the dyntrans chunk size again, because NetBSD/cats seemed less stable with full size chunks. :( NetBSD/sgimips 3.0 can now run :-) (With release 0.3.8, only NetBSD/sgimips 2.1 worked, not 3.0.) ============== RELEASE 0.4.0 ==============
1 | #ifndef CPU_X86_H |
2 | #define CPU_X86_H |
3 | |
4 | /* |
5 | * Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions are met: |
9 | * |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
28 | * SUCH DAMAGE. |
29 | * |
30 | * |
31 | * $Id: cpu_x86.h,v 1.47 2006/04/17 11:06:46 debug Exp $ |
32 | * |
33 | * x86 (including AMD64) cpu dependent stuff. |
34 | */ |
35 | |
36 | #include "misc.h" |
37 | |
38 | |
39 | struct cpu_family; |
40 | |
41 | #define N_X86_REGS 16 |
42 | |
43 | #define x86_reg_names { \ |
44 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \ |
45 | "08", "09", "10", "11", "12", "13", "14", "15" } |
46 | #define x86_reg_names_bytes { \ |
47 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" } |
48 | |
49 | #define X86_R_AX 0 |
50 | #define X86_R_CX 1 |
51 | #define X86_R_DX 2 |
52 | #define X86_R_BX 3 |
53 | #define X86_R_SP 4 |
54 | #define X86_R_BP 5 |
55 | #define X86_R_SI 6 |
56 | #define X86_R_DI 7 |
57 | |
58 | #define N_X86_SEGS 8 |
59 | /* (All of these 8 are not actually used.) */ |
60 | |
61 | #define X86_S_ES 0 |
62 | #define X86_S_CS 1 |
63 | #define X86_S_SS 2 |
64 | #define X86_S_DS 3 |
65 | #define X86_S_FS 4 |
66 | #define X86_S_GS 5 |
67 | |
68 | #define x86_seg_names { "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7" } |
69 | |
70 | #define N_X86_CREGS 8 |
71 | |
72 | #define N_X86_DREGS 8 |
73 | |
74 | #define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" } |
75 | #define N_X86_CONDS 8 |
76 | |
77 | #define X86_MODEL_8086 1 |
78 | #define X86_MODEL_80286 2 |
79 | #define X86_MODEL_80386 3 |
80 | #define X86_MODEL_80486 4 |
81 | #define X86_MODEL_PENTIUM 5 |
82 | #define X86_MODEL_AMD64 6 |
83 | |
84 | struct x86_model { |
85 | int model_number; |
86 | char *name; |
87 | }; |
88 | |
89 | #define x86_models { \ |
90 | { X86_MODEL_8086, "8086" }, \ |
91 | { X86_MODEL_80286, "80286" }, \ |
92 | { X86_MODEL_80386, "80386" }, \ |
93 | { X86_MODEL_80486, "80486" }, \ |
94 | { X86_MODEL_PENTIUM, "PENTIUM" }, \ |
95 | { X86_MODEL_AMD64, "AMD64" }, \ |
96 | { 0, NULL } \ |
97 | } |
98 | |
99 | #define X86_N_IC_ARGS 3 |
100 | #define X86_INSTR_ALIGNMENT_SHIFT 0 |
101 | #define X86_IC_ENTRIES_SHIFT 12 |
102 | #define X86_IC_ENTRIES_PER_PAGE (1 << X86_IC_ENTRIES_SHIFT) |
103 | #define X86_PC_TO_IC_ENTRY(a) ((a) & (X86_IC_ENTRIES_PER_PAGE-1)) |
104 | #define X86_ADDR_TO_PAGENR(a) ((a) >> X86_IC_ENTRIES_SHIFT) |
105 | |
106 | #define X86_L2N 17 |
107 | #define X86_L3N 18 |
108 | |
109 | DYNTRANS_MISC_DECLARATIONS(x86,X86,uint64_t) |
110 | DYNTRANS_MISC64_DECLARATIONS(x86,X86,uint8_t) |
111 | |
112 | #define X86_MAX_VPH_TLB_ENTRIES 128 |
113 | |
114 | struct descriptor_cache { |
115 | int valid; |
116 | int default_op_size; |
117 | int access_rights; |
118 | int descr_type; |
119 | int readable; |
120 | int writable; |
121 | int granularity; |
122 | uint64_t base; |
123 | uint64_t limit; |
124 | }; |
125 | |
126 | |
127 | struct x86_cpu { |
128 | struct x86_model model; |
129 | |
130 | int halted; |
131 | int interrupt_asserted; |
132 | |
133 | int cursegment; /* NOTE: 0..N_X86_SEGS-1 */ |
134 | int seg_override; /* 0 or 1 */ |
135 | |
136 | uint64_t tsc; /* time stamp counter */ |
137 | |
138 | uint64_t gdtr; /* global descriptor table */ |
139 | uint32_t gdtr_limit; |
140 | uint64_t idtr; /* interrupt descriptor table */ |
141 | uint32_t idtr_limit; |
142 | |
143 | uint16_t tr; /* task register */ |
144 | uint64_t tr_base; |
145 | uint32_t tr_limit; |
146 | uint16_t ldtr; /* local descriptor table register */ |
147 | uint64_t ldtr_base; |
148 | uint32_t ldtr_limit; |
149 | |
150 | uint64_t rflags; |
151 | uint64_t cr[N_X86_CREGS]; /* control registers */ |
152 | uint64_t dr[N_X86_DREGS]; /* debug registers */ |
153 | |
154 | uint16_t s[N_X86_SEGS]; /* segment selectors */ |
155 | struct descriptor_cache descr_cache[N_X86_SEGS]; |
156 | |
157 | uint64_t r[N_X86_REGS]; /* GPRs */ |
158 | |
159 | /* FPU: */ |
160 | uint16_t fpu_sw; /* status word */ |
161 | uint16_t fpu_cw; /* control word */ |
162 | |
163 | /* MSRs: */ |
164 | uint64_t efer; |
165 | |
166 | |
167 | /* |
168 | * Instruction translation cache and Virtual->Physical->Host |
169 | * address translation: |
170 | */ |
171 | DYNTRANS_ITC(x86) |
172 | VPH_TLBS(x86,X86) |
173 | VPH32(x86,X86,uint64_t,uint8_t) |
174 | VPH64(x86,X86,uint8_t) |
175 | }; |
176 | |
177 | |
178 | #define X86_FLAGS_CF (1) /* Carry Flag */ |
179 | #define X86_FLAGS_PF (4) /* Parity Flag */ |
180 | #define X86_FLAGS_AF (16) /* Adjust/AuxilaryCarry Flag */ |
181 | #define X86_FLAGS_ZF (64) /* Zero Flag */ |
182 | #define X86_FLAGS_SF (128) /* Sign Flag */ |
183 | #define X86_FLAGS_TF (256) /* Trap Flag */ |
184 | #define X86_FLAGS_IF (512) /* Interrupt Enable Flag */ |
185 | #define X86_FLAGS_DF (1024) /* Direction Flag */ |
186 | #define X86_FLAGS_OF (2048) /* Overflow Flag */ |
187 | /* Bits 12 and 13 are I/O Privilege Level */ |
188 | #define X86_FLAGS_NT (1<<14) /* Nested Task Flag */ |
189 | #define X86_FLAGS_RF (1<<16) /* Resume Flag */ |
190 | #define X86_FLAGS_VM (1<<17) /* VM86 Flag */ |
191 | #define X86_FLAGS_AC (1<<18) /* Alignment Check */ |
192 | #define X86_FLAGS_VIF (1<<19) /* ? */ |
193 | #define X86_FLAGS_VIP (1<<20) /* ? */ |
194 | #define X86_FLAGS_ID (1<<21) /* CPUID present */ |
195 | |
196 | #define X86_CR0_PE 0x00000001 /* Protection Enable */ |
197 | #define X86_CR0_MP 0x00000002 |
198 | #define X86_CR0_EM 0x00000004 |
199 | #define X86_CR0_TS 0x00000008 |
200 | #define X86_CR0_ET 0x00000010 |
201 | #define X86_CR0_NE 0x00000020 |
202 | #define X86_CR0_WP 0x00010000 |
203 | #define X86_CR0_AM 0x00040000 |
204 | #define X86_CR0_NW 0x20000000 |
205 | #define X86_CR0_CD 0x40000000 |
206 | #define X86_CR0_PG 0x80000000 /* Paging Enable */ |
207 | |
208 | #define X86_CR4_OSXMEX 0x00000400 |
209 | #define X86_CR4_OSFXSR 0x00000200 |
210 | #define X86_CR4_PCE 0x00000100 |
211 | #define X86_CR4_PGE 0x00000080 |
212 | #define X86_CR4_MCE 0x00000040 |
213 | #define X86_CR4_PAE 0x00000020 |
214 | #define X86_CR4_PSE 0x00000010 |
215 | #define X86_CR4_DE 0x00000008 |
216 | #define X86_CR4_TSD 0x00000004 /* Time Stamp Disable */ |
217 | #define X86_CR4_PVI 0x00000002 |
218 | #define X86_CR4_VME 0x00000001 |
219 | |
220 | /* EFER bits: */ |
221 | #define X86_EFER_FFXSR 0x00004000 |
222 | #define X86_EFER_LMSLE 0x00002000 |
223 | #define X86_EFER_NXE 0x00000800 |
224 | #define X86_EFER_LMA 0x00000400 |
225 | #define X86_EFER_LME 0x00000100 /* Long Mode (64-bit) */ |
226 | #define X86_EFER_SCE 0x00000001 |
227 | |
228 | /* CPUID feature bits: */ |
229 | #define X86_CPUID_ECX_ETPRD 0x00004000 |
230 | #define X86_CPUID_ECX_CX16 0x00002000 /* cmpxchg16b */ |
231 | #define X86_CPUID_ECX_CID 0x00000400 |
232 | #define X86_CPUID_ECX_TM2 0x00000100 |
233 | #define X86_CPUID_ECX_EST 0x00000080 |
234 | #define X86_CPUID_ECX_DSCPL 0x00000010 |
235 | #define X86_CPUID_ECX_MON 0x00000004 |
236 | #define X86_CPUID_ECX_SSE3 0x00000001 |
237 | #define X86_CPUID_EDX_PBE 0x80000000 /* pending break event */ |
238 | #define X86_CPUID_EDX_IA64 0x40000000 |
239 | #define X86_CPUID_EDX_TM1 0x20000000 /* thermal interrupt */ |
240 | #define X86_CPUID_EDX_HTT 0x10000000 /* hyper threading */ |
241 | #define X86_CPUID_EDX_SS 0x08000000 /* self-snoop */ |
242 | #define X86_CPUID_EDX_SSE2 0x04000000 |
243 | #define X86_CPUID_EDX_SSE 0x02000000 |
244 | #define X86_CPUID_EDX_FXSR 0x01000000 |
245 | #define X86_CPUID_EDX_MMX 0x00800000 |
246 | #define X86_CPUID_EDX_ACPI 0x00400000 |
247 | #define X86_CPUID_EDX_DTES 0x00200000 |
248 | #define X86_CPUID_EDX_CLFL 0x00080000 |
249 | #define X86_CPUID_EDX_PSN 0x00040000 |
250 | #define X86_CPUID_EDX_PSE36 0x00020000 |
251 | #define X86_CPUID_EDX_PAT 0x00010000 |
252 | #define X86_CPUID_EDX_CMOV 0x00008000 |
253 | #define X86_CPUID_EDX_MCA 0x00004000 |
254 | #define X86_CPUID_EDX_PGE 0x00002000 /* global bit in PDE/PTE */ |
255 | #define X86_CPUID_EDX_MTRR 0x00001000 |
256 | #define X86_CPUID_EDX_SEP 0x00000800 /* sysenter/sysexit */ |
257 | #define X86_CPUID_EDX_APIC 0x00000200 |
258 | #define X86_CPUID_EDX_CX8 0x00000100 /* cmpxchg8b */ |
259 | #define X86_CPUID_EDX_MCE 0x00000080 |
260 | #define X86_CPUID_EDX_PAE 0x00000040 |
261 | #define X86_CPUID_EDX_MSR 0x00000020 |
262 | #define X86_CPUID_EDX_TSC 0x00000010 |
263 | #define X86_CPUID_EDX_PSE 0x00000008 |
264 | #define X86_CPUID_EDX_DE 0x00000004 |
265 | #define X86_CPUID_EDX_VME 0x00000002 |
266 | #define X86_CPUID_EDX_FPU 0x00000001 |
267 | |
268 | /* Extended CPUID flags: */ |
269 | #define X86_CPUID_EXT_ECX_CR8D 0x00000010 |
270 | #define X86_CPUID_EXT_ECX_CMP 0x00000002 |
271 | #define X86_CPUID_EXT_ECX_AHF64 0x00000001 |
272 | #define X86_CPUID_EXT_EDX_LM 0x20000000 /* AMD64 Long Mode */ |
273 | #define X86_CPUID_EXT_EDX_FFXSR 0x02000000 |
274 | /* TODO: Many bits are duplicated in the Extended CPUID bits! */ |
275 | |
276 | #define X86_IO_BASE 0x1000000000ULL |
277 | |
278 | /* Privilege level in the lowest 2 bits of a selector: */ |
279 | #define X86_PL_MASK 0x0003 |
280 | #define X86_RING0 0 |
281 | #define X86_RING1 1 |
282 | #define X86_RING2 2 |
283 | #define X86_RING3 3 |
284 | |
285 | #define DESCR_TYPE_CODE 1 |
286 | #define DESCR_TYPE_DATA 2 |
287 | |
288 | |
289 | #define LONG_MODE (cpu->cd.x86.efer & X86_EFER_LME) |
290 | #define PROTECTED_MODE (cpu->cd.x86.cr[0] & X86_CR0_PE) |
291 | #define REAL_MODE (!PROTECTED_MODE) |
292 | |
293 | |
294 | /* cpu_x86.c: */ |
295 | void reload_segment_descriptor(struct cpu *cpu, int segnr, int selector, |
296 | uint64_t *curpcp); |
297 | int x86_interrupt(struct cpu *cpu, int nr, int errcode); |
298 | int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
299 | unsigned char *data, size_t len, int writeflag, int cache_flags); |
300 | void x86_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
301 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
302 | void x8632_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
303 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
304 | void x86_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
305 | void x8632_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
306 | void x86_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
307 | void x8632_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
308 | void x86_init_64bit_dummy_tables(struct cpu *cpu); |
309 | int x86_cpu_family_init(struct cpu_family *); |
310 | |
311 | |
312 | /* memory_x86.c: */ |
313 | int x86_translate_address(struct cpu *cpu, uint64_t vaddr, |
314 | uint64_t *return_addr, int flags); |
315 | |
316 | #endif /* CPU_X86_H */ |
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