/[gxemul]/trunk/src/include/cpu_x86.h
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revision 21 by dpavlin, Mon Oct 8 16:19:23 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 2  Line 2 
2  #define CPU_X86_H  #define CPU_X86_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_x86.h,v 1.39 2005/11/16 21:15:19 debug Exp $   *  $Id: cpu_x86.h,v 1.43 2006/02/13 04:23:25 debug Exp $
32     *
33     *  x86 (including AMD64) cpu dependent stuff.
34   */   */
35    
36  #include "misc.h"  #include "misc.h"
# Line 101  struct x86_model { Line 103  struct x86_model {
103  #define X86_PC_TO_IC_ENTRY(a)           ((a) & (X86_IC_ENTRIES_PER_PAGE-1))  #define X86_PC_TO_IC_ENTRY(a)           ((a) & (X86_IC_ENTRIES_PER_PAGE-1))
104  #define X86_ADDR_TO_PAGENR(a)           ((a) >> X86_IC_ENTRIES_SHIFT)  #define X86_ADDR_TO_PAGENR(a)           ((a) >> X86_IC_ENTRIES_SHIFT)
105    
106  struct x86_instr_call {  DYNTRANS_MISC_DECLARATIONS(x86,X86,uint64_t)
         void    (*f)(struct cpu *, struct x86_instr_call *);  
         int     len;  
         size_t  arg[X86_N_IC_ARGS];  
 };  
   
 /*  Translation cache struct for each physical page:  */  
 struct x86_tc_physpage {  
         struct x86_instr_call ics[X86_IC_ENTRIES_PER_PAGE + 1];  
         uint32_t        next_ofs;       /*  or 0 for end of chain  */  
         int             flags;  
         uint64_t        physaddr;  
 };  
107    
108  #define X86_N_VPH_ENTRIES               1048576  #define X86_MAX_VPH_TLB_ENTRIES         128
   
 #define X86_MAX_VPH_TLB_ENTRIES         256  
 struct x86_vpg_tlb_entry {  
         uint8_t         valid;  
         uint8_t         writeflag;  
         unsigned char   *host_page;  
         int64_t         timestamp;  
         uint64_t        vaddr_page;  
         uint64_t        paddr_page;  
 };  
109    
110  struct descriptor_cache {  struct descriptor_cache {
111          int             valid;          int             valid;
# Line 181  struct x86_cpu { Line 161  struct x86_cpu {
161    
162    
163          /*          /*
164           *  Instruction translation cache:           *  Instruction translation cache and Virtual->Physical->Host
165             *  address translation:
166           */           */
167            DYNTRANS_ITC(x86)
168          /*  cur_ic_page is a pointer to an array of X86_IC_ENTRIES_PER_PAGE          VPH_TLBS(x86,X86)
169              instruction call entries. next_ic points to the next such          VPH32(x86,X86,uint64_t,uint8_t)
170              call to be executed.  */          VPH64(x86,X86,uint8_t)
         struct x86_tc_physpage  *cur_physpage;  
         struct x86_instr_call   *cur_ic_page;  
         struct x86_instr_call   *next_ic;  
   
         void                    (*combination_check)(struct cpu *,  
                                     struct x86_instr_call *, int low_addr);  
   
         /*  
          *  Virtual -> physical -> host address translation:  
          *  
          *  host_load and host_store point to arrays of X86_N_VPH_ENTRIES  
          *  pointers (to host pages); phys_addr points to an array of  
          *  X86_N_VPH_ENTRIES uint32_t.  
          */  
   
         struct x86_vpg_tlb_entry        vph_tlb_entry[X86_MAX_VPH_TLB_ENTRIES];  
         unsigned char                   *host_load[X86_N_VPH_ENTRIES];  
         unsigned char                   *host_store[X86_N_VPH_ENTRIES];  
         uint32_t                        phys_addr[X86_N_VPH_ENTRIES];  
         struct x86_tc_physpage          *phys_page[X86_N_VPH_ENTRIES];  
   
         uint32_t                        phystranslation[X86_N_VPH_ENTRIES/32];  
         uint8_t                         vaddr_to_tlbindex[X86_N_VPH_ENTRIES];  
171  };  };
172    
173    
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