/[gxemul]/trunk/src/include/cpu_x86.h
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Annotation of /trunk/src/include/cpu_x86.h

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Revision 28 - (hide annotations)
Mon Oct 8 16:20:26 2007 UTC (13 years, 3 months ago) by dpavlin
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File size: 10213 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 dpavlin 4 #ifndef CPU_X86_H
2     #define CPU_X86_H
3    
4     /*
5 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 dpavlin 4 *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 28 * $Id: cpu_x86.h,v 1.49 2006/07/16 13:32:28 debug Exp $
32 dpavlin 22 *
33     * x86 (including AMD64) cpu dependent stuff.
34 dpavlin 4 */
35    
36     #include "misc.h"
37    
38    
39     struct cpu_family;
40    
41     #define N_X86_REGS 16
42    
43     #define x86_reg_names { \
44     "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \
45     "08", "09", "10", "11", "12", "13", "14", "15" }
46 dpavlin 6 #define x86_reg_names_bytes { \
47     "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" }
48 dpavlin 4
49     #define X86_R_AX 0
50     #define X86_R_CX 1
51     #define X86_R_DX 2
52     #define X86_R_BX 3
53     #define X86_R_SP 4
54     #define X86_R_BP 5
55     #define X86_R_SI 6
56     #define X86_R_DI 7
57    
58     #define N_X86_SEGS 8
59     /* (All of these 8 are not actually used.) */
60    
61     #define X86_S_ES 0
62     #define X86_S_CS 1
63     #define X86_S_SS 2
64     #define X86_S_DS 3
65     #define X86_S_FS 4
66     #define X86_S_GS 5
67    
68 dpavlin 6 #define x86_seg_names { "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7" }
69 dpavlin 4
70     #define N_X86_CREGS 8
71    
72 dpavlin 6 #define N_X86_DREGS 8
73    
74 dpavlin 4 #define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" }
75     #define N_X86_CONDS 8
76    
77     #define X86_MODEL_8086 1
78 dpavlin 6 #define X86_MODEL_80286 2
79     #define X86_MODEL_80386 3
80     #define X86_MODEL_80486 4
81     #define X86_MODEL_PENTIUM 5
82     #define X86_MODEL_AMD64 6
83 dpavlin 4
84     struct x86_model {
85     int model_number;
86     char *name;
87     };
88    
89     #define x86_models { \
90     { X86_MODEL_8086, "8086" }, \
91 dpavlin 6 { X86_MODEL_80286, "80286" }, \
92 dpavlin 4 { X86_MODEL_80386, "80386" }, \
93 dpavlin 6 { X86_MODEL_80486, "80486" }, \
94 dpavlin 4 { X86_MODEL_PENTIUM, "PENTIUM" }, \
95     { X86_MODEL_AMD64, "AMD64" }, \
96     { 0, NULL } \
97     }
98    
99 dpavlin 12 #define X86_N_IC_ARGS 3
100     #define X86_INSTR_ALIGNMENT_SHIFT 0
101     #define X86_IC_ENTRIES_SHIFT 12
102     #define X86_IC_ENTRIES_PER_PAGE (1 << X86_IC_ENTRIES_SHIFT)
103     #define X86_PC_TO_IC_ENTRY(a) ((a) & (X86_IC_ENTRIES_PER_PAGE-1))
104     #define X86_ADDR_TO_PAGENR(a) ((a) >> X86_IC_ENTRIES_SHIFT)
105 dpavlin 4
106 dpavlin 24 #define X86_L2N 17
107     #define X86_L3N 18
108    
109 dpavlin 22 DYNTRANS_MISC_DECLARATIONS(x86,X86,uint64_t)
110 dpavlin 24 DYNTRANS_MISC64_DECLARATIONS(x86,X86,uint8_t)
111 dpavlin 12
112 dpavlin 22 #define X86_MAX_VPH_TLB_ENTRIES 128
113 dpavlin 12
114 dpavlin 6 struct descriptor_cache {
115     int valid;
116     int default_op_size;
117     int access_rights;
118     int descr_type;
119     int readable;
120     int writable;
121     int granularity;
122     uint64_t base;
123     uint64_t limit;
124     };
125    
126    
127 dpavlin 4 struct x86_cpu {
128     struct x86_model model;
129    
130 dpavlin 6 int halted;
131     int interrupt_asserted;
132 dpavlin 4
133 dpavlin 6 int cursegment; /* NOTE: 0..N_X86_SEGS-1 */
134     int seg_override; /* 0 or 1 */
135 dpavlin 4
136 dpavlin 6 uint64_t tsc; /* time stamp counter */
137    
138     uint64_t gdtr; /* global descriptor table */
139     uint32_t gdtr_limit;
140     uint64_t idtr; /* interrupt descriptor table */
141     uint32_t idtr_limit;
142    
143     uint16_t tr; /* task register */
144     uint64_t tr_base;
145     uint32_t tr_limit;
146     uint16_t ldtr; /* local descriptor table register */
147     uint64_t ldtr_base;
148     uint32_t ldtr_limit;
149    
150 dpavlin 4 uint64_t rflags;
151 dpavlin 6 uint64_t cr[N_X86_CREGS]; /* control registers */
152     uint64_t dr[N_X86_DREGS]; /* debug registers */
153 dpavlin 4
154 dpavlin 6 uint16_t s[N_X86_SEGS]; /* segment selectors */
155     struct descriptor_cache descr_cache[N_X86_SEGS];
156    
157     uint64_t r[N_X86_REGS]; /* GPRs */
158    
159     /* FPU: */
160     uint16_t fpu_sw; /* status word */
161     uint16_t fpu_cw; /* control word */
162    
163     /* MSRs: */
164     uint64_t efer;
165 dpavlin 12
166    
167     /*
168 dpavlin 22 * Instruction translation cache and Virtual->Physical->Host
169     * address translation:
170 dpavlin 12 */
171 dpavlin 22 DYNTRANS_ITC(x86)
172     VPH_TLBS(x86,X86)
173     VPH32(x86,X86,uint64_t,uint8_t)
174     VPH64(x86,X86,uint8_t)
175 dpavlin 4 };
176    
177    
178     #define X86_FLAGS_CF (1) /* Carry Flag */
179     #define X86_FLAGS_PF (4) /* Parity Flag */
180     #define X86_FLAGS_AF (16) /* Adjust/AuxilaryCarry Flag */
181     #define X86_FLAGS_ZF (64) /* Zero Flag */
182     #define X86_FLAGS_SF (128) /* Sign Flag */
183     #define X86_FLAGS_TF (256) /* Trap Flag */
184     #define X86_FLAGS_IF (512) /* Interrupt Enable Flag */
185     #define X86_FLAGS_DF (1024) /* Direction Flag */
186     #define X86_FLAGS_OF (2048) /* Overflow Flag */
187     /* Bits 12 and 13 are I/O Privilege Level */
188     #define X86_FLAGS_NT (1<<14) /* Nested Task Flag */
189     #define X86_FLAGS_RF (1<<16) /* Resume Flag */
190     #define X86_FLAGS_VM (1<<17) /* VM86 Flag */
191 dpavlin 6 #define X86_FLAGS_AC (1<<18) /* Alignment Check */
192     #define X86_FLAGS_VIF (1<<19) /* ? */
193     #define X86_FLAGS_VIP (1<<20) /* ? */
194     #define X86_FLAGS_ID (1<<21) /* CPUID present */
195 dpavlin 4
196 dpavlin 6 #define X86_CR0_PE 0x00000001 /* Protection Enable */
197     #define X86_CR0_MP 0x00000002
198     #define X86_CR0_EM 0x00000004
199     #define X86_CR0_TS 0x00000008
200     #define X86_CR0_ET 0x00000010
201     #define X86_CR0_NE 0x00000020
202     #define X86_CR0_WP 0x00010000
203     #define X86_CR0_AM 0x00040000
204     #define X86_CR0_NW 0x20000000
205     #define X86_CR0_CD 0x40000000
206     #define X86_CR0_PG 0x80000000 /* Paging Enable */
207 dpavlin 4
208 dpavlin 6 #define X86_CR4_OSXMEX 0x00000400
209     #define X86_CR4_OSFXSR 0x00000200
210     #define X86_CR4_PCE 0x00000100
211     #define X86_CR4_PGE 0x00000080
212     #define X86_CR4_MCE 0x00000040
213     #define X86_CR4_PAE 0x00000020
214     #define X86_CR4_PSE 0x00000010
215     #define X86_CR4_DE 0x00000008
216     #define X86_CR4_TSD 0x00000004 /* Time Stamp Disable */
217     #define X86_CR4_PVI 0x00000002
218     #define X86_CR4_VME 0x00000001
219    
220     /* EFER bits: */
221     #define X86_EFER_FFXSR 0x00004000
222     #define X86_EFER_LMSLE 0x00002000
223     #define X86_EFER_NXE 0x00000800
224     #define X86_EFER_LMA 0x00000400
225     #define X86_EFER_LME 0x00000100 /* Long Mode (64-bit) */
226     #define X86_EFER_SCE 0x00000001
227    
228     /* CPUID feature bits: */
229     #define X86_CPUID_ECX_ETPRD 0x00004000
230     #define X86_CPUID_ECX_CX16 0x00002000 /* cmpxchg16b */
231     #define X86_CPUID_ECX_CID 0x00000400
232     #define X86_CPUID_ECX_TM2 0x00000100
233     #define X86_CPUID_ECX_EST 0x00000080
234     #define X86_CPUID_ECX_DSCPL 0x00000010
235     #define X86_CPUID_ECX_MON 0x00000004
236     #define X86_CPUID_ECX_SSE3 0x00000001
237     #define X86_CPUID_EDX_PBE 0x80000000 /* pending break event */
238     #define X86_CPUID_EDX_IA64 0x40000000
239     #define X86_CPUID_EDX_TM1 0x20000000 /* thermal interrupt */
240     #define X86_CPUID_EDX_HTT 0x10000000 /* hyper threading */
241     #define X86_CPUID_EDX_SS 0x08000000 /* self-snoop */
242     #define X86_CPUID_EDX_SSE2 0x04000000
243     #define X86_CPUID_EDX_SSE 0x02000000
244     #define X86_CPUID_EDX_FXSR 0x01000000
245     #define X86_CPUID_EDX_MMX 0x00800000
246     #define X86_CPUID_EDX_ACPI 0x00400000
247     #define X86_CPUID_EDX_DTES 0x00200000
248     #define X86_CPUID_EDX_CLFL 0x00080000
249     #define X86_CPUID_EDX_PSN 0x00040000
250     #define X86_CPUID_EDX_PSE36 0x00020000
251     #define X86_CPUID_EDX_PAT 0x00010000
252     #define X86_CPUID_EDX_CMOV 0x00008000
253     #define X86_CPUID_EDX_MCA 0x00004000
254     #define X86_CPUID_EDX_PGE 0x00002000 /* global bit in PDE/PTE */
255     #define X86_CPUID_EDX_MTRR 0x00001000
256     #define X86_CPUID_EDX_SEP 0x00000800 /* sysenter/sysexit */
257     #define X86_CPUID_EDX_APIC 0x00000200
258     #define X86_CPUID_EDX_CX8 0x00000100 /* cmpxchg8b */
259     #define X86_CPUID_EDX_MCE 0x00000080
260     #define X86_CPUID_EDX_PAE 0x00000040
261     #define X86_CPUID_EDX_MSR 0x00000020
262     #define X86_CPUID_EDX_TSC 0x00000010
263     #define X86_CPUID_EDX_PSE 0x00000008
264     #define X86_CPUID_EDX_DE 0x00000004
265     #define X86_CPUID_EDX_VME 0x00000002
266     #define X86_CPUID_EDX_FPU 0x00000001
267    
268     /* Extended CPUID flags: */
269     #define X86_CPUID_EXT_ECX_CR8D 0x00000010
270     #define X86_CPUID_EXT_ECX_CMP 0x00000002
271     #define X86_CPUID_EXT_ECX_AHF64 0x00000001
272     #define X86_CPUID_EXT_EDX_LM 0x20000000 /* AMD64 Long Mode */
273     #define X86_CPUID_EXT_EDX_FFXSR 0x02000000
274     /* TODO: Many bits are duplicated in the Extended CPUID bits! */
275    
276     #define X86_IO_BASE 0x1000000000ULL
277    
278     /* Privilege level in the lowest 2 bits of a selector: */
279     #define X86_PL_MASK 0x0003
280     #define X86_RING0 0
281     #define X86_RING1 1
282     #define X86_RING2 2
283     #define X86_RING3 3
284    
285     #define DESCR_TYPE_CODE 1
286     #define DESCR_TYPE_DATA 2
287    
288    
289 dpavlin 24 #define LONG_MODE (cpu->cd.x86.efer & X86_EFER_LME)
290 dpavlin 6 #define PROTECTED_MODE (cpu->cd.x86.cr[0] & X86_CR0_PE)
291     #define REAL_MODE (!PROTECTED_MODE)
292    
293 dpavlin 24
294 dpavlin 4 /* cpu_x86.c: */
295 dpavlin 6 void reload_segment_descriptor(struct cpu *cpu, int segnr, int selector,
296     uint64_t *curpcp);
297     int x86_interrupt(struct cpu *cpu, int nr, int errcode);
298 dpavlin 28 int x86_run_instr(struct cpu *cpu);
299     int x8632_run_instr(struct cpu *cpu);
300 dpavlin 4 int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
301     unsigned char *data, size_t len, int writeflag, int cache_flags);
302 dpavlin 20 void x86_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
303     unsigned char *host_page, int writeflag, uint64_t paddr_page);
304     void x8632_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
305     unsigned char *host_page, int writeflag, uint64_t paddr_page);
306     void x86_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
307     void x8632_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
308     void x86_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
309     void x8632_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
310 dpavlin 24 void x86_init_64bit_dummy_tables(struct cpu *cpu);
311 dpavlin 4 int x86_cpu_family_init(struct cpu_family *);
312    
313 dpavlin 20
314 dpavlin 14 /* memory_x86.c: */
315 dpavlin 26 int x86_translate_v2p(struct cpu *cpu, uint64_t vaddr,
316 dpavlin 14 uint64_t *return_addr, int flags);
317 dpavlin 4
318     #endif /* CPU_X86_H */

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