/[gxemul]/trunk/src/include/cpu_x86.h
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Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 dpavlin 4 #ifndef CPU_X86_H
2     #define CPU_X86_H
3    
4     /*
5 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 dpavlin 4 *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 22 * $Id: cpu_x86.h,v 1.43 2006/02/13 04:23:25 debug Exp $
32     *
33     * x86 (including AMD64) cpu dependent stuff.
34 dpavlin 4 */
35    
36     #include "misc.h"
37    
38    
39     struct cpu_family;
40    
41     #define N_X86_REGS 16
42    
43     #define x86_reg_names { \
44     "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \
45     "08", "09", "10", "11", "12", "13", "14", "15" }
46 dpavlin 6 #define x86_reg_names_bytes { \
47     "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" }
48 dpavlin 4
49     #define X86_R_AX 0
50     #define X86_R_CX 1
51     #define X86_R_DX 2
52     #define X86_R_BX 3
53     #define X86_R_SP 4
54     #define X86_R_BP 5
55     #define X86_R_SI 6
56     #define X86_R_DI 7
57    
58     #define N_X86_SEGS 8
59     /* (All of these 8 are not actually used.) */
60    
61     #define X86_S_ES 0
62     #define X86_S_CS 1
63     #define X86_S_SS 2
64     #define X86_S_DS 3
65     #define X86_S_FS 4
66     #define X86_S_GS 5
67    
68 dpavlin 6 #define x86_seg_names { "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7" }
69 dpavlin 4
70     #define N_X86_CREGS 8
71    
72 dpavlin 6 #define N_X86_DREGS 8
73    
74 dpavlin 4 #define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" }
75     #define N_X86_CONDS 8
76    
77     #define X86_MODEL_8086 1
78 dpavlin 6 #define X86_MODEL_80286 2
79     #define X86_MODEL_80386 3
80     #define X86_MODEL_80486 4
81     #define X86_MODEL_PENTIUM 5
82     #define X86_MODEL_AMD64 6
83 dpavlin 4
84     struct x86_model {
85     int model_number;
86     char *name;
87     };
88    
89     #define x86_models { \
90     { X86_MODEL_8086, "8086" }, \
91 dpavlin 6 { X86_MODEL_80286, "80286" }, \
92 dpavlin 4 { X86_MODEL_80386, "80386" }, \
93 dpavlin 6 { X86_MODEL_80486, "80486" }, \
94 dpavlin 4 { X86_MODEL_PENTIUM, "PENTIUM" }, \
95     { X86_MODEL_AMD64, "AMD64" }, \
96     { 0, NULL } \
97     }
98    
99 dpavlin 12 #define X86_N_IC_ARGS 3
100     #define X86_INSTR_ALIGNMENT_SHIFT 0
101     #define X86_IC_ENTRIES_SHIFT 12
102     #define X86_IC_ENTRIES_PER_PAGE (1 << X86_IC_ENTRIES_SHIFT)
103     #define X86_PC_TO_IC_ENTRY(a) ((a) & (X86_IC_ENTRIES_PER_PAGE-1))
104     #define X86_ADDR_TO_PAGENR(a) ((a) >> X86_IC_ENTRIES_SHIFT)
105 dpavlin 4
106 dpavlin 22 DYNTRANS_MISC_DECLARATIONS(x86,X86,uint64_t)
107 dpavlin 12
108 dpavlin 22 #define X86_MAX_VPH_TLB_ENTRIES 128
109 dpavlin 12
110 dpavlin 6 struct descriptor_cache {
111     int valid;
112     int default_op_size;
113     int access_rights;
114     int descr_type;
115     int readable;
116     int writable;
117     int granularity;
118     uint64_t base;
119     uint64_t limit;
120     };
121    
122    
123 dpavlin 4 struct x86_cpu {
124     struct x86_model model;
125    
126 dpavlin 6 int halted;
127     int interrupt_asserted;
128 dpavlin 4
129 dpavlin 6 int cursegment; /* NOTE: 0..N_X86_SEGS-1 */
130     int seg_override; /* 0 or 1 */
131 dpavlin 4
132 dpavlin 6 uint64_t tsc; /* time stamp counter */
133    
134     uint64_t gdtr; /* global descriptor table */
135     uint32_t gdtr_limit;
136     uint64_t idtr; /* interrupt descriptor table */
137     uint32_t idtr_limit;
138    
139     uint16_t tr; /* task register */
140     uint64_t tr_base;
141     uint32_t tr_limit;
142     uint16_t ldtr; /* local descriptor table register */
143     uint64_t ldtr_base;
144     uint32_t ldtr_limit;
145    
146 dpavlin 4 uint64_t rflags;
147 dpavlin 6 uint64_t cr[N_X86_CREGS]; /* control registers */
148     uint64_t dr[N_X86_DREGS]; /* debug registers */
149 dpavlin 4
150 dpavlin 6 uint16_t s[N_X86_SEGS]; /* segment selectors */
151     struct descriptor_cache descr_cache[N_X86_SEGS];
152    
153     uint64_t r[N_X86_REGS]; /* GPRs */
154    
155     /* FPU: */
156     uint16_t fpu_sw; /* status word */
157     uint16_t fpu_cw; /* control word */
158    
159     /* MSRs: */
160     uint64_t efer;
161 dpavlin 12
162    
163     /*
164 dpavlin 22 * Instruction translation cache and Virtual->Physical->Host
165     * address translation:
166 dpavlin 12 */
167 dpavlin 22 DYNTRANS_ITC(x86)
168     VPH_TLBS(x86,X86)
169     VPH32(x86,X86,uint64_t,uint8_t)
170     VPH64(x86,X86,uint8_t)
171 dpavlin 4 };
172    
173    
174     #define X86_FLAGS_CF (1) /* Carry Flag */
175     #define X86_FLAGS_PF (4) /* Parity Flag */
176     #define X86_FLAGS_AF (16) /* Adjust/AuxilaryCarry Flag */
177     #define X86_FLAGS_ZF (64) /* Zero Flag */
178     #define X86_FLAGS_SF (128) /* Sign Flag */
179     #define X86_FLAGS_TF (256) /* Trap Flag */
180     #define X86_FLAGS_IF (512) /* Interrupt Enable Flag */
181     #define X86_FLAGS_DF (1024) /* Direction Flag */
182     #define X86_FLAGS_OF (2048) /* Overflow Flag */
183     /* Bits 12 and 13 are I/O Privilege Level */
184     #define X86_FLAGS_NT (1<<14) /* Nested Task Flag */
185     #define X86_FLAGS_RF (1<<16) /* Resume Flag */
186     #define X86_FLAGS_VM (1<<17) /* VM86 Flag */
187 dpavlin 6 #define X86_FLAGS_AC (1<<18) /* Alignment Check */
188     #define X86_FLAGS_VIF (1<<19) /* ? */
189     #define X86_FLAGS_VIP (1<<20) /* ? */
190     #define X86_FLAGS_ID (1<<21) /* CPUID present */
191 dpavlin 4
192 dpavlin 6 #define X86_CR0_PE 0x00000001 /* Protection Enable */
193     #define X86_CR0_MP 0x00000002
194     #define X86_CR0_EM 0x00000004
195     #define X86_CR0_TS 0x00000008
196     #define X86_CR0_ET 0x00000010
197     #define X86_CR0_NE 0x00000020
198     #define X86_CR0_WP 0x00010000
199     #define X86_CR0_AM 0x00040000
200     #define X86_CR0_NW 0x20000000
201     #define X86_CR0_CD 0x40000000
202     #define X86_CR0_PG 0x80000000 /* Paging Enable */
203 dpavlin 4
204 dpavlin 6 #define X86_CR4_OSXMEX 0x00000400
205     #define X86_CR4_OSFXSR 0x00000200
206     #define X86_CR4_PCE 0x00000100
207     #define X86_CR4_PGE 0x00000080
208     #define X86_CR4_MCE 0x00000040
209     #define X86_CR4_PAE 0x00000020
210     #define X86_CR4_PSE 0x00000010
211     #define X86_CR4_DE 0x00000008
212     #define X86_CR4_TSD 0x00000004 /* Time Stamp Disable */
213     #define X86_CR4_PVI 0x00000002
214     #define X86_CR4_VME 0x00000001
215    
216     /* EFER bits: */
217     #define X86_EFER_FFXSR 0x00004000
218     #define X86_EFER_LMSLE 0x00002000
219     #define X86_EFER_NXE 0x00000800
220     #define X86_EFER_LMA 0x00000400
221     #define X86_EFER_LME 0x00000100 /* Long Mode (64-bit) */
222     #define X86_EFER_SCE 0x00000001
223    
224     /* CPUID feature bits: */
225     #define X86_CPUID_ECX_ETPRD 0x00004000
226     #define X86_CPUID_ECX_CX16 0x00002000 /* cmpxchg16b */
227     #define X86_CPUID_ECX_CID 0x00000400
228     #define X86_CPUID_ECX_TM2 0x00000100
229     #define X86_CPUID_ECX_EST 0x00000080
230     #define X86_CPUID_ECX_DSCPL 0x00000010
231     #define X86_CPUID_ECX_MON 0x00000004
232     #define X86_CPUID_ECX_SSE3 0x00000001
233     #define X86_CPUID_EDX_PBE 0x80000000 /* pending break event */
234     #define X86_CPUID_EDX_IA64 0x40000000
235     #define X86_CPUID_EDX_TM1 0x20000000 /* thermal interrupt */
236     #define X86_CPUID_EDX_HTT 0x10000000 /* hyper threading */
237     #define X86_CPUID_EDX_SS 0x08000000 /* self-snoop */
238     #define X86_CPUID_EDX_SSE2 0x04000000
239     #define X86_CPUID_EDX_SSE 0x02000000
240     #define X86_CPUID_EDX_FXSR 0x01000000
241     #define X86_CPUID_EDX_MMX 0x00800000
242     #define X86_CPUID_EDX_ACPI 0x00400000
243     #define X86_CPUID_EDX_DTES 0x00200000
244     #define X86_CPUID_EDX_CLFL 0x00080000
245     #define X86_CPUID_EDX_PSN 0x00040000
246     #define X86_CPUID_EDX_PSE36 0x00020000
247     #define X86_CPUID_EDX_PAT 0x00010000
248     #define X86_CPUID_EDX_CMOV 0x00008000
249     #define X86_CPUID_EDX_MCA 0x00004000
250     #define X86_CPUID_EDX_PGE 0x00002000 /* global bit in PDE/PTE */
251     #define X86_CPUID_EDX_MTRR 0x00001000
252     #define X86_CPUID_EDX_SEP 0x00000800 /* sysenter/sysexit */
253     #define X86_CPUID_EDX_APIC 0x00000200
254     #define X86_CPUID_EDX_CX8 0x00000100 /* cmpxchg8b */
255     #define X86_CPUID_EDX_MCE 0x00000080
256     #define X86_CPUID_EDX_PAE 0x00000040
257     #define X86_CPUID_EDX_MSR 0x00000020
258     #define X86_CPUID_EDX_TSC 0x00000010
259     #define X86_CPUID_EDX_PSE 0x00000008
260     #define X86_CPUID_EDX_DE 0x00000004
261     #define X86_CPUID_EDX_VME 0x00000002
262     #define X86_CPUID_EDX_FPU 0x00000001
263    
264     /* Extended CPUID flags: */
265     #define X86_CPUID_EXT_ECX_CR8D 0x00000010
266     #define X86_CPUID_EXT_ECX_CMP 0x00000002
267     #define X86_CPUID_EXT_ECX_AHF64 0x00000001
268     #define X86_CPUID_EXT_EDX_LM 0x20000000 /* AMD64 Long Mode */
269     #define X86_CPUID_EXT_EDX_FFXSR 0x02000000
270     /* TODO: Many bits are duplicated in the Extended CPUID bits! */
271    
272     #define X86_IO_BASE 0x1000000000ULL
273    
274     /* Privilege level in the lowest 2 bits of a selector: */
275     #define X86_PL_MASK 0x0003
276     #define X86_RING0 0
277     #define X86_RING1 1
278     #define X86_RING2 2
279     #define X86_RING3 3
280    
281     #define DESCR_TYPE_CODE 1
282     #define DESCR_TYPE_DATA 2
283    
284    
285     #define PROTECTED_MODE (cpu->cd.x86.cr[0] & X86_CR0_PE)
286     #define REAL_MODE (!PROTECTED_MODE)
287    
288 dpavlin 4 /* cpu_x86.c: */
289 dpavlin 6 void reload_segment_descriptor(struct cpu *cpu, int segnr, int selector,
290     uint64_t *curpcp);
291     int x86_interrupt(struct cpu *cpu, int nr, int errcode);
292 dpavlin 4 int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
293     unsigned char *data, size_t len, int writeflag, int cache_flags);
294 dpavlin 20 void x86_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
295     unsigned char *host_page, int writeflag, uint64_t paddr_page);
296     void x8632_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
297     unsigned char *host_page, int writeflag, uint64_t paddr_page);
298     void x86_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
299     void x8632_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
300     void x86_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
301     void x8632_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
302 dpavlin 4 int x86_cpu_family_init(struct cpu_family *);
303    
304 dpavlin 20
305 dpavlin 14 /* memory_x86.c: */
306     int x86_translate_address(struct cpu *cpu, uint64_t vaddr,
307     uint64_t *return_addr, int flags);
308 dpavlin 4
309     #endif /* CPU_X86_H */

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