src/include/cpu_x86.h

#ifndef CPU_X86_H
#define CPU_X86_H

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_x86.h,v 1.35 2005/10/27 14:01:15 debug Exp $
 */

#include "misc.h"


struct cpu_family;

#define N_X86_REGS              16

#define x86_reg_names           {                       \
        "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \
        "08", "09", "10", "11", "12", "13", "14", "15" }
#define x86_reg_names_bytes     {                       \
        "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" }

#define X86_R_AX        0
#define X86_R_CX        1
#define X86_R_DX        2
#define X86_R_BX        3
#define X86_R_SP        4
#define X86_R_BP        5
#define X86_R_SI        6
#define X86_R_DI        7

#define N_X86_SEGS              8
/*  (All of these 8 are not actually used.)  */

#define X86_S_ES        0
#define X86_S_CS        1
#define X86_S_SS        2
#define X86_S_DS        3
#define X86_S_FS        4
#define X86_S_GS        5

#define x86_seg_names   { "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7" }

#define N_X86_CREGS             8

#define N_X86_DREGS             8

#define x86_cond_names  { "o", "b", "z", "be", "s", "p", "l", "le" }
#define N_X86_CONDS             8

#define X86_MODEL_8086          1
#define X86_MODEL_80286         2
#define X86_MODEL_80386         3
#define X86_MODEL_80486         4
#define X86_MODEL_PENTIUM       5
#define X86_MODEL_AMD64         6

struct x86_model {
        int             model_number;
        char            *name;
};

#define x86_models {                                                    \
        { X86_MODEL_8086, "8086" },                                     \
        { X86_MODEL_80286, "80286" },                                   \
        { X86_MODEL_80386, "80386" },                                   \
        { X86_MODEL_80486, "80486" },                                   \
        { X86_MODEL_PENTIUM, "PENTIUM" },                               \
        { X86_MODEL_AMD64, "AMD64" },                                   \
        { 0, NULL }                                                     \
        }

#define X86_N_IC_ARGS                   3
#define X86_INSTR_ALIGNMENT_SHIFT       0
#define X86_IC_ENTRIES_SHIFT            12
#define X86_IC_ENTRIES_PER_PAGE         (1 << X86_IC_ENTRIES_SHIFT)
#define X86_PC_TO_IC_ENTRY(a)           ((a) & (X86_IC_ENTRIES_PER_PAGE-1))
#define X86_ADDR_TO_PAGENR(a)           ((a) >> X86_IC_ENTRIES_SHIFT)

struct x86_instr_call {
        void    (*f)(struct cpu *, struct x86_instr_call *);
        size_t  arg[X86_N_IC_ARGS];
};

/*  Translation cache struct for each physical page:  */
struct x86_tc_physpage {
        struct x86_instr_call ics[X86_IC_ENTRIES_PER_PAGE + 1];
        uint32_t        next_ofs;       /*  or 0 for end of chain  */
        int             flags;
        uint64_t        physaddr;
};

#define X86_N_VPH_ENTRIES               1048576

#define X86_MAX_VPH_TLB_ENTRIES         256
struct x86_vpg_tlb_entry {
        int             valid;
        int             writeflag;
        int64_t         timestamp;
        unsigned char   *host_page;
        uint64_t        vaddr_page;
        uint64_t        paddr_page;
};

struct descriptor_cache {
        int             valid;
        int             default_op_size;
        int             access_rights;
        int             descr_type;
        int             readable;
        int             writable;
        int             granularity;
        uint64_t        base;
        uint64_t        limit;
};


struct x86_cpu {
        struct x86_model model;

        int             halted;
        int             interrupt_asserted;

        int             cursegment;     /*  NOTE: 0..N_X86_SEGS-1  */
        int             seg_override;   /*  0 or 1  */

        uint64_t        tsc;            /*  time stamp counter  */

        uint64_t        gdtr;           /*  global descriptor table */
        uint32_t        gdtr_limit;
        uint64_t        idtr;           /*  interrupt descriptor table  */
        uint32_t        idtr_limit;

        uint16_t        tr;             /*  task register  */
        uint64_t        tr_base;
        uint32_t        tr_limit;
        uint16_t        ldtr;           /*  local descriptor table register  */
        uint64_t        ldtr_base;
        uint32_t        ldtr_limit;

        uint64_t        rflags;
        uint64_t        cr[N_X86_CREGS];        /*  control registers  */
        uint64_t        dr[N_X86_DREGS];        /*  debug registers  */

        uint16_t        s[N_X86_SEGS];          /*  segment selectors  */
        struct descriptor_cache descr_cache[N_X86_SEGS];

        uint64_t        r[N_X86_REGS];          /*  GPRs  */

        /*  FPU:  */
        uint16_t        fpu_sw;         /*  status word  */
        uint16_t        fpu_cw;         /*  control word  */

        /*  MSRs:  */
        uint64_t        efer;


        /*
         *  Instruction translation cache:
         */

        /*  cur_ic_page is a pointer to an array of X86_IC_ENTRIES_PER_PAGE
            instruction call entries. next_ic points to the next such
            call to be executed.  */
        struct x86_tc_physpage  *cur_physpage;
        struct x86_instr_call   *cur_ic_page;
        struct x86_instr_call   *next_ic;


        /*
         *  Virtual -> physical -> host address translation:
         *
         *  host_load and host_store point to arrays of X86_N_VPH_ENTRIES
         *  pointers (to host pages); phys_addr points to an array of
         *  X86_N_VPH_ENTRIES uint32_t.
         */

        struct x86_vpg_tlb_entry        vph_tlb_entry[X86_MAX_VPH_TLB_ENTRIES];
        unsigned char                   *host_load[X86_N_VPH_ENTRIES];
        unsigned char                   *host_store[X86_N_VPH_ENTRIES];
        uint32_t                        phys_addr[X86_N_VPH_ENTRIES];
        struct x86_tc_physpage          *phys_page[X86_N_VPH_ENTRIES];

        uint32_t                        phystranslation[X86_N_VPH_ENTRIES/32];
};


#define X86_FLAGS_CF    (1)             /*  Carry Flag  */
#define X86_FLAGS_PF    (4)             /*  Parity Flag  */
#define X86_FLAGS_AF    (16)            /*  Adjust/AuxilaryCarry Flag  */
#define X86_FLAGS_ZF    (64)            /*  Zero Flag  */
#define X86_FLAGS_SF    (128)           /*  Sign Flag  */
#define X86_FLAGS_TF    (256)           /*  Trap Flag  */
#define X86_FLAGS_IF    (512)           /*  Interrupt Enable Flag  */
#define X86_FLAGS_DF    (1024)          /*  Direction Flag  */
#define X86_FLAGS_OF    (2048)          /*  Overflow Flag  */
/*  Bits 12 and 13 are I/O Privilege Level  */
#define X86_FLAGS_NT    (1<<14)         /*  Nested Task Flag  */
#define X86_FLAGS_RF    (1<<16)         /*  Resume Flag  */
#define X86_FLAGS_VM    (1<<17)         /*  VM86 Flag  */
#define X86_FLAGS_AC    (1<<18)         /*  Alignment Check  */
#define X86_FLAGS_VIF   (1<<19)         /*  ?  */
#define X86_FLAGS_VIP   (1<<20)         /*  ?  */
#define X86_FLAGS_ID    (1<<21)         /*  CPUID present  */

#define X86_CR0_PE      0x00000001      /*  Protection Enable  */
#define X86_CR0_MP      0x00000002
#define X86_CR0_EM      0x00000004
#define X86_CR0_TS      0x00000008
#define X86_CR0_ET      0x00000010
#define X86_CR0_NE      0x00000020
#define X86_CR0_WP      0x00010000
#define X86_CR0_AM      0x00040000
#define X86_CR0_NW      0x20000000
#define X86_CR0_CD      0x40000000
#define X86_CR0_PG      0x80000000      /*  Paging Enable  */

#define X86_CR4_OSXMEX  0x00000400
#define X86_CR4_OSFXSR  0x00000200
#define X86_CR4_PCE     0x00000100
#define X86_CR4_PGE     0x00000080
#define X86_CR4_MCE     0x00000040
#define X86_CR4_PAE     0x00000020
#define X86_CR4_PSE     0x00000010
#define X86_CR4_DE      0x00000008
#define X86_CR4_TSD     0x00000004      /*  Time Stamp Disable  */
#define X86_CR4_PVI     0x00000002
#define X86_CR4_VME     0x00000001

/*  EFER bits:  */
#define X86_EFER_FFXSR  0x00004000
#define X86_EFER_LMSLE  0x00002000
#define X86_EFER_NXE    0x00000800
#define X86_EFER_LMA    0x00000400
#define X86_EFER_LME    0x00000100      /*  Long Mode (64-bit)  */
#define X86_EFER_SCE    0x00000001

/*  CPUID feature bits:  */
#define X86_CPUID_ECX_ETPRD     0x00004000
#define X86_CPUID_ECX_CX16      0x00002000      /*  cmpxchg16b  */
#define X86_CPUID_ECX_CID       0x00000400
#define X86_CPUID_ECX_TM2       0x00000100
#define X86_CPUID_ECX_EST       0x00000080
#define X86_CPUID_ECX_DSCPL     0x00000010
#define X86_CPUID_ECX_MON       0x00000004
#define X86_CPUID_ECX_SSE3      0x00000001
#define X86_CPUID_EDX_PBE       0x80000000      /*  pending break event  */
#define X86_CPUID_EDX_IA64      0x40000000
#define X86_CPUID_EDX_TM1       0x20000000      /*  thermal interrupt  */
#define X86_CPUID_EDX_HTT       0x10000000      /*  hyper threading  */
#define X86_CPUID_EDX_SS        0x08000000      /*  self-snoop  */
#define X86_CPUID_EDX_SSE2      0x04000000
#define X86_CPUID_EDX_SSE       0x02000000
#define X86_CPUID_EDX_FXSR      0x01000000
#define X86_CPUID_EDX_MMX       0x00800000
#define X86_CPUID_EDX_ACPI      0x00400000
#define X86_CPUID_EDX_DTES      0x00200000
#define X86_CPUID_EDX_CLFL      0x00080000
#define X86_CPUID_EDX_PSN       0x00040000
#define X86_CPUID_EDX_PSE36     0x00020000
#define X86_CPUID_EDX_PAT       0x00010000
#define X86_CPUID_EDX_CMOV      0x00008000
#define X86_CPUID_EDX_MCA       0x00004000
#define X86_CPUID_EDX_PGE       0x00002000      /*  global bit in PDE/PTE  */
#define X86_CPUID_EDX_MTRR      0x00001000
#define X86_CPUID_EDX_SEP       0x00000800      /*  sysenter/sysexit  */
#define X86_CPUID_EDX_APIC      0x00000200
#define X86_CPUID_EDX_CX8       0x00000100      /*  cmpxchg8b  */
#define X86_CPUID_EDX_MCE       0x00000080
#define X86_CPUID_EDX_PAE       0x00000040
#define X86_CPUID_EDX_MSR       0x00000020
#define X86_CPUID_EDX_TSC       0x00000010
#define X86_CPUID_EDX_PSE       0x00000008
#define X86_CPUID_EDX_DE        0x00000004
#define X86_CPUID_EDX_VME       0x00000002
#define X86_CPUID_EDX_FPU       0x00000001

/*  Extended CPUID flags:  */
#define X86_CPUID_EXT_ECX_CR8D  0x00000010
#define X86_CPUID_EXT_ECX_CMP   0x00000002
#define X86_CPUID_EXT_ECX_AHF64 0x00000001
#define X86_CPUID_EXT_EDX_LM    0x20000000      /*  AMD64 Long Mode  */
#define X86_CPUID_EXT_EDX_FFXSR 0x02000000
/*  TODO: Many bits are duplicated in the Extended CPUID bits!  */

#define X86_IO_BASE     0x1000000000ULL

/*  Privilege level in the lowest 2 bits of a selector:  */
#define X86_PL_MASK             0x0003
#define X86_RING0               0
#define X86_RING1               1
#define X86_RING2               2
#define X86_RING3               3

#define DESCR_TYPE_CODE         1
#define DESCR_TYPE_DATA         2


#define PROTECTED_MODE          (cpu->cd.x86.cr[0] & X86_CR0_PE)
#define REAL_MODE               (!PROTECTED_MODE)

/*  cpu_x86.c:  */
void reload_segment_descriptor(struct cpu *cpu, int segnr, int selector,
        uint64_t *curpcp);
int x86_interrupt(struct cpu *cpu, int nr, int errcode);
int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int x86_cpu_family_init(struct cpu_family *);

/*  memory_x86.c:  */
int x86_translate_address(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);

#endif  /*  CPU_X86_H  */
1	dpavlin	4	#ifndef CPU_X86_H
2			#define CPU_X86_H
3
4			/*
5			* Copyright (C) 2005 Anders Gavare. All rights reserved.
6			*
7			* Redistribution and use in source and binary forms, with or without
8			* modification, are permitted provided that the following conditions are met:
9			*
10			* 1. Redistributions of source code must retain the above copyright
11			* notice, this list of conditions and the following disclaimer.
12			* 2. Redistributions in binary form must reproduce the above copyright
13			* notice, this list of conditions and the following disclaimer in the
14			* documentation and/or other materials provided with the distribution.
15			* 3. The name of the author may not be used to endorse or promote products
16			* derived from this software without specific prior written permission.
17			*
18			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28			* SUCH DAMAGE.
29			*
30			*
31	dpavlin	18	* $Id: cpu_x86.h,v 1.35 2005/10/27 14:01:15 debug Exp $
32	dpavlin	4	*/
33
34			#include "misc.h"
35
36
37			struct cpu_family;
38
39			#define N_X86_REGS 16
40
41			#define x86_reg_names { \
42			"ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \
43			"08", "09", "10", "11", "12", "13", "14", "15" }
44	dpavlin	6	#define x86_reg_names_bytes { \
45			"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" }
46	dpavlin	4
47			#define X86_R_AX 0
48			#define X86_R_CX 1
49			#define X86_R_DX 2
50			#define X86_R_BX 3
51			#define X86_R_SP 4
52			#define X86_R_BP 5
53			#define X86_R_SI 6
54			#define X86_R_DI 7
55
56			#define N_X86_SEGS 8
57			/* (All of these 8 are not actually used.) */
58
59			#define X86_S_ES 0
60			#define X86_S_CS 1
61			#define X86_S_SS 2
62			#define X86_S_DS 3
63			#define X86_S_FS 4
64			#define X86_S_GS 5
65
66	dpavlin	6	#define x86_seg_names { "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7" }
67	dpavlin	4
68			#define N_X86_CREGS 8
69
70	dpavlin	6	#define N_X86_DREGS 8
71
72	dpavlin	4	#define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" }
73			#define N_X86_CONDS 8
74
75			#define X86_MODEL_8086 1
76	dpavlin	6	#define X86_MODEL_80286 2
77			#define X86_MODEL_80386 3
78			#define X86_MODEL_80486 4
79			#define X86_MODEL_PENTIUM 5
80			#define X86_MODEL_AMD64 6
81	dpavlin	4
82			struct x86_model {
83			int model_number;
84			char *name;
85			};
86
87			#define x86_models { \
88			{ X86_MODEL_8086, "8086" }, \
89	dpavlin	6	{ X86_MODEL_80286, "80286" }, \
90	dpavlin	4	{ X86_MODEL_80386, "80386" }, \
91	dpavlin	6	{ X86_MODEL_80486, "80486" }, \
92	dpavlin	4	{ X86_MODEL_PENTIUM, "PENTIUM" }, \
93			{ X86_MODEL_AMD64, "AMD64" }, \
94			{ 0, NULL } \
95			}
96
97	dpavlin	12	#define X86_N_IC_ARGS 3
98			#define X86_INSTR_ALIGNMENT_SHIFT 0
99			#define X86_IC_ENTRIES_SHIFT 12
100			#define X86_IC_ENTRIES_PER_PAGE (1 << X86_IC_ENTRIES_SHIFT)
101			#define X86_PC_TO_IC_ENTRY(a) ((a) & (X86_IC_ENTRIES_PER_PAGE-1))
102			#define X86_ADDR_TO_PAGENR(a) ((a) >> X86_IC_ENTRIES_SHIFT)
103	dpavlin	4
104	dpavlin	12	struct x86_instr_call {
105			void (f)(struct cpu , struct x86_instr_call *);
106			size_t arg[X86_N_IC_ARGS];
107			};
108
109			/* Translation cache struct for each physical page: */
110			struct x86_tc_physpage {
111	dpavlin	18	struct x86_instr_call ics[X86_IC_ENTRIES_PER_PAGE + 1];
112	dpavlin	12	uint32_t next_ofs; /* or 0 for end of chain */
113	dpavlin	18	int flags;
114	dpavlin	12	uint64_t physaddr;
115			};
116
117			#define X86_N_VPH_ENTRIES 1048576
118
119			#define X86_MAX_VPH_TLB_ENTRIES 256
120			struct x86_vpg_tlb_entry {
121			int valid;
122			int writeflag;
123			int64_t timestamp;
124			unsigned char *host_page;
125			uint64_t vaddr_page;
126			uint64_t paddr_page;
127			};
128
129	dpavlin	6	struct descriptor_cache {
130			int valid;
131			int default_op_size;
132			int access_rights;
133			int descr_type;
134			int readable;
135			int writable;
136			int granularity;
137			uint64_t base;
138			uint64_t limit;
139			};
140
141
142	dpavlin	4	struct x86_cpu {
143			struct x86_model model;
144
145	dpavlin	6	int halted;
146			int interrupt_asserted;
147	dpavlin	4
148	dpavlin	6	int cursegment; /* NOTE: 0..N_X86_SEGS-1 */
149			int seg_override; /* 0 or 1 */
150	dpavlin	4
151	dpavlin	6	uint64_t tsc; /* time stamp counter */
152
153			uint64_t gdtr; /* global descriptor table */
154			uint32_t gdtr_limit;
155			uint64_t idtr; /* interrupt descriptor table */
156			uint32_t idtr_limit;
157
158			uint16_t tr; /* task register */
159			uint64_t tr_base;
160			uint32_t tr_limit;
161			uint16_t ldtr; /* local descriptor table register */
162			uint64_t ldtr_base;
163			uint32_t ldtr_limit;
164
165	dpavlin	4	uint64_t rflags;
166	dpavlin	6	uint64_t cr[N_X86_CREGS]; /* control registers */
167			uint64_t dr[N_X86_DREGS]; /* debug registers */
168	dpavlin	4
169	dpavlin	6	uint16_t s[N_X86_SEGS]; /* segment selectors */
170			struct descriptor_cache descr_cache[N_X86_SEGS];
171
172			uint64_t r[N_X86_REGS]; /* GPRs */
173
174			/* FPU: */
175			uint16_t fpu_sw; /* status word */
176			uint16_t fpu_cw; /* control word */
177
178			/* MSRs: */
179			uint64_t efer;
180	dpavlin	12
181
182			/*
183			* Instruction translation cache:
184			*/
185
186			/* cur_ic_page is a pointer to an array of X86_IC_ENTRIES_PER_PAGE
187			instruction call entries. next_ic points to the next such
188			call to be executed. */
189			struct x86_tc_physpage *cur_physpage;
190			struct x86_instr_call *cur_ic_page;
191			struct x86_instr_call *next_ic;
192
193
194			/*
195			* Virtual -> physical -> host address translation:
196			*
197			* host_load and host_store point to arrays of X86_N_VPH_ENTRIES
198			* pointers (to host pages); phys_addr points to an array of
199			* X86_N_VPH_ENTRIES uint32_t.
200			*/
201
202			struct x86_vpg_tlb_entry vph_tlb_entry[X86_MAX_VPH_TLB_ENTRIES];
203			unsigned char *host_load[X86_N_VPH_ENTRIES];
204			unsigned char *host_store[X86_N_VPH_ENTRIES];
205			uint32_t phys_addr[X86_N_VPH_ENTRIES];
206			struct x86_tc_physpage *phys_page[X86_N_VPH_ENTRIES];
207	dpavlin	18
208			uint32_t phystranslation[X86_N_VPH_ENTRIES/32];
209	dpavlin	4	};
210
211
212			#define X86_FLAGS_CF (1) /* Carry Flag */
213			#define X86_FLAGS_PF (4) /* Parity Flag */
214			#define X86_FLAGS_AF (16) /* Adjust/AuxilaryCarry Flag */
215			#define X86_FLAGS_ZF (64) /* Zero Flag */
216			#define X86_FLAGS_SF (128) /* Sign Flag */
217			#define X86_FLAGS_TF (256) /* Trap Flag */
218			#define X86_FLAGS_IF (512) /* Interrupt Enable Flag */
219			#define X86_FLAGS_DF (1024) /* Direction Flag */
220			#define X86_FLAGS_OF (2048) /* Overflow Flag */
221			/* Bits 12 and 13 are I/O Privilege Level */
222			#define X86_FLAGS_NT (1<<14) /* Nested Task Flag */
223			#define X86_FLAGS_RF (1<<16) /* Resume Flag */
224			#define X86_FLAGS_VM (1<<17) /* VM86 Flag */
225	dpavlin	6	#define X86_FLAGS_AC (1<<18) /* Alignment Check */
226			#define X86_FLAGS_VIF (1<<19) /* ? */
227			#define X86_FLAGS_VIP (1<<20) /* ? */
228			#define X86_FLAGS_ID (1<<21) /* CPUID present */
229	dpavlin	4
230	dpavlin	6	#define X86_CR0_PE 0x00000001 /* Protection Enable */
231			#define X86_CR0_MP 0x00000002
232			#define X86_CR0_EM 0x00000004
233			#define X86_CR0_TS 0x00000008
234			#define X86_CR0_ET 0x00000010
235			#define X86_CR0_NE 0x00000020
236			#define X86_CR0_WP 0x00010000
237			#define X86_CR0_AM 0x00040000
238			#define X86_CR0_NW 0x20000000
239			#define X86_CR0_CD 0x40000000
240			#define X86_CR0_PG 0x80000000 /* Paging Enable */
241	dpavlin	4
242	dpavlin	6	#define X86_CR4_OSXMEX 0x00000400
243			#define X86_CR4_OSFXSR 0x00000200
244			#define X86_CR4_PCE 0x00000100
245			#define X86_CR4_PGE 0x00000080
246			#define X86_CR4_MCE 0x00000040
247			#define X86_CR4_PAE 0x00000020
248			#define X86_CR4_PSE 0x00000010
249			#define X86_CR4_DE 0x00000008
250			#define X86_CR4_TSD 0x00000004 /* Time Stamp Disable */
251			#define X86_CR4_PVI 0x00000002
252			#define X86_CR4_VME 0x00000001
253
254			/* EFER bits: */
255			#define X86_EFER_FFXSR 0x00004000
256			#define X86_EFER_LMSLE 0x00002000
257			#define X86_EFER_NXE 0x00000800
258			#define X86_EFER_LMA 0x00000400
259			#define X86_EFER_LME 0x00000100 /* Long Mode (64-bit) */
260			#define X86_EFER_SCE 0x00000001
261
262			/* CPUID feature bits: */
263			#define X86_CPUID_ECX_ETPRD 0x00004000
264			#define X86_CPUID_ECX_CX16 0x00002000 /* cmpxchg16b */
265			#define X86_CPUID_ECX_CID 0x00000400
266			#define X86_CPUID_ECX_TM2 0x00000100
267			#define X86_CPUID_ECX_EST 0x00000080
268			#define X86_CPUID_ECX_DSCPL 0x00000010
269			#define X86_CPUID_ECX_MON 0x00000004
270			#define X86_CPUID_ECX_SSE3 0x00000001
271			#define X86_CPUID_EDX_PBE 0x80000000 /* pending break event */
272			#define X86_CPUID_EDX_IA64 0x40000000
273			#define X86_CPUID_EDX_TM1 0x20000000 /* thermal interrupt */
274			#define X86_CPUID_EDX_HTT 0x10000000 /* hyper threading */
275			#define X86_CPUID_EDX_SS 0x08000000 /* self-snoop */
276			#define X86_CPUID_EDX_SSE2 0x04000000
277			#define X86_CPUID_EDX_SSE 0x02000000
278			#define X86_CPUID_EDX_FXSR 0x01000000
279			#define X86_CPUID_EDX_MMX 0x00800000
280			#define X86_CPUID_EDX_ACPI 0x00400000
281			#define X86_CPUID_EDX_DTES 0x00200000
282			#define X86_CPUID_EDX_CLFL 0x00080000
283			#define X86_CPUID_EDX_PSN 0x00040000
284			#define X86_CPUID_EDX_PSE36 0x00020000
285			#define X86_CPUID_EDX_PAT 0x00010000
286			#define X86_CPUID_EDX_CMOV 0x00008000
287			#define X86_CPUID_EDX_MCA 0x00004000
288			#define X86_CPUID_EDX_PGE 0x00002000 /* global bit in PDE/PTE */
289			#define X86_CPUID_EDX_MTRR 0x00001000
290			#define X86_CPUID_EDX_SEP 0x00000800 /* sysenter/sysexit */
291			#define X86_CPUID_EDX_APIC 0x00000200
292			#define X86_CPUID_EDX_CX8 0x00000100 /* cmpxchg8b */
293			#define X86_CPUID_EDX_MCE 0x00000080
294			#define X86_CPUID_EDX_PAE 0x00000040
295			#define X86_CPUID_EDX_MSR 0x00000020
296			#define X86_CPUID_EDX_TSC 0x00000010
297			#define X86_CPUID_EDX_PSE 0x00000008
298			#define X86_CPUID_EDX_DE 0x00000004
299			#define X86_CPUID_EDX_VME 0x00000002
300			#define X86_CPUID_EDX_FPU 0x00000001
301
302			/* Extended CPUID flags: */
303			#define X86_CPUID_EXT_ECX_CR8D 0x00000010
304			#define X86_CPUID_EXT_ECX_CMP 0x00000002
305			#define X86_CPUID_EXT_ECX_AHF64 0x00000001
306			#define X86_CPUID_EXT_EDX_LM 0x20000000 /* AMD64 Long Mode */
307			#define X86_CPUID_EXT_EDX_FFXSR 0x02000000
308			/* TODO: Many bits are duplicated in the Extended CPUID bits! */
309
310			#define X86_IO_BASE 0x1000000000ULL
311
312			/* Privilege level in the lowest 2 bits of a selector: */
313			#define X86_PL_MASK 0x0003
314			#define X86_RING0 0
315			#define X86_RING1 1
316			#define X86_RING2 2
317			#define X86_RING3 3
318
319			#define DESCR_TYPE_CODE 1
320			#define DESCR_TYPE_DATA 2
321
322
323			#define PROTECTED_MODE (cpu->cd.x86.cr[0] & X86_CR0_PE)
324			#define REAL_MODE (!PROTECTED_MODE)
325
326	dpavlin	4	/* cpu_x86.c: */
327	dpavlin	6	void reload_segment_descriptor(struct cpu *cpu, int segnr, int selector,
328			uint64_t *curpcp);
329			int x86_interrupt(struct cpu *cpu, int nr, int errcode);
330	dpavlin	4	int x86_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
331			unsigned char *data, size_t len, int writeflag, int cache_flags);
332			int x86_cpu_family_init(struct cpu_family *);
333
334	dpavlin	14	/* memory_x86.c: */
335			int x86_translate_address(struct cpu *cpu, uint64_t vaddr,
336			uint64_t *return_addr, int flags);
337	dpavlin	4
338			#endif /* CPU_X86_H */