/[gxemul]/trunk/src/include/cpu_transputer.h
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Contents of /trunk/src/include/cpu_transputer.h

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Revision 30 - (show annotations)
Mon Oct 8 16:20:40 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 10477 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1325 2006/08/15 15:38:37 debug Exp $
20060723	More Transputer instructions (pfix, nfix, opr, mint, ldl, ldlp,
		eqc, rev, ajw, stl, stlf, sthf, sub, ldnl, ldnlp, ldpi, move,
		wcnt, add, bcnt).
		Adding more SPARC instructions (andcc, addcc, bl, rdpr).
		Progress on the igsfb framebuffer used by NetBSD/netwinder.
		Enabling 8-bit fills in dev_fb.
		NetBSD/netwinder 3.0.1 can now run from a disk image :-)
20060724	Cleanup/performance fix for 64-bit virtual translation table
		updates (by removing the "timestamp" stuff). A full NetBSD/pmax
		3.0.1 install for R4400 has dropped from 667 seconds to 584 :)
		Fixing the igsfb "almost vga" color (it is 24-bit, not 18-bit).
		Adding some MIPS instruction combinations (3*lw, and 3*addu).
		The 8048 keyboard now turns off interrupt enable between the
		KBR_ACK and the KBR_RSTDONE, to work better with Linux 2.6.
		Not causing PPC DEC interrupts if PPC_NO_DEC is set for a
		specific CPU; NetBSD/bebox gets slightly further than before.
		Adding some more SPARC instructions: branches, udiv.
20060725	Refreshing dev_pckbc.c a little.
		Cleanups for the SH emulation mode, and adding the first
		"compact" (16-bit) instructions: various simple movs, nop,
		shll, stc, or, ldc.
20060726	Adding dummy "pcn" (AMD PCnet NIC) PCI glue.
20060727	Various cleanups; removing stuff from cpu.h, such as
		running_translated (not really meaningful anymore), and
		page flags (breaking into the debugger clears all translations
		anyway).
		Minor MIPS instruction combination updates.
20060807	Expanding the 3*sw and 3*lw MIPS instruction combinations to
		work with 2* and 4* too, resulting in a minor performance gain.
		Implementing a usleep hack for the RM52xx/MIPS32/MIPS64 "wait"
		instruction (when emulating 1 cpu).
20060808	Experimenting with some more MIPS instruction combinations.
		Implementing support for showing a (hardcoded 12x22) text
		cursor in igsfb.
20060809	Simplifying the NetBSD/evbmips (Malta) install instructions
		somewhat (by using a NetBSD/pmax ramdisk install kernel).
20060812	Experimenting more with the MIPS 'wait' instruction.
		PCI configuration register writes can now be handled, which
		allow PCI IDE controllers to work with NetBSD/Malta 3.0.1 and
		NetBSD/cobalt 3.0.1. (Previously only NetBSD 2.1 worked.)
20060813	Updating dev_gt.c based on numbers from Alec Voropay, to enable
		Linux 2.6 to use PCI on Malta.
		Continuing on Algor interrupt stuff.
20060814	Adding support for routing ISA interrupts to two different
		interrupts, making it possible to run NetBSD/algor :-)
20060814-15	Testing for the release.

==============  RELEASE 0.4.2  ==============
1 #ifndef CPU_TRANSPUTER_H
2 #define CPU_TRANSPUTER_H
3
4 /*
5 * Copyright (C) 2006 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_transputer.h,v 1.6 2006/07/23 15:42:20 debug Exp $
32 */
33
34 #include "misc.h"
35
36
37 struct cpu_family;
38
39
40 /* TRANSPUTER CPU types: */
41 struct transputer_cpu_type_def {
42 char *name;
43 int bits; /* 16 or 32 */
44 int onchip_ram; /* 2048 or 4096 bytes */
45 int features;
46 };
47
48 /*
49 * Features of various transputer processors according to
50 * http://www.enlight.ru/docs/cpu/t-puters/talp/app_g.txt:
51 *
52 * (TODO: Add the T9000 too?)
53 */
54
55 #define T_T4_FP 1 /* T4 floating point */
56 #define T_T8_FP 2 /* T8 floating point */
57 #define T_2D_BLOCK 4 /* 2D Block Move instruction */
58 #define T_FMUL 8 /* FMUL instruction */
59 #define T_DUP 16 /* DUP instruction */
60 #define T_WSUBDB 32 /* WSUBDB instruction */
61 #define T_CRC 64 /* CRC instruction */
62 #define T_BITCOUNT 128 /* BITCOUNT instruction */
63 #define T_FPTESTERR 256 /* FPTESTERR instruction */
64 #define T_DEBUG 512 /* Debug capabilities */
65
66 #define TRANSPUTER_CPU_TYPE_DEFS { \
67 { "T212", 16, 2048, 0 }, \
68 { "T222", 16, 4096, 0 }, \
69 { "T225", 16, 4096, T_DUP | T_WSUBDB | T_CRC | T_BITCOUNT | \
70 T_DEBUG }, \
71 { "T414", 32, 2048, T_FMUL | T_T4_FP }, \
72 { "T425", 32, 4096, T_T4_FP | T_2D_BLOCK | T_FMUL | T_WSUBDB | \
73 T_DUP | T_CRC | T_BITCOUNT | T_FPTESTERR | \
74 T_DEBUG }, \
75 { "T800", 32, 4096, T_T8_FP | T_2D_BLOCK | T_FMUL | T_WSUBDB | \
76 T_DUP | T_CRC | T_BITCOUNT | T_FPTESTERR }, \
77 { "T801", 32, 4096, T_T8_FP | T_2D_BLOCK | T_FMUL | T_WSUBDB | \
78 T_DUP | T_CRC | T_BITCOUNT | T_FPTESTERR }, \
79 { "T805", 32, 4096, T_T8_FP | T_2D_BLOCK | T_FMUL | T_WSUBDB | \
80 T_DUP | T_CRC | T_BITCOUNT | T_FPTESTERR | \
81 T_DEBUG }, \
82 { NULL, 0, 0, 0 } }
83
84 #define TRANSPUTER_INSTRUCTIONS { \
85 /* 0X */ "j", /* jump */ \
86 /* 1X */ "ldlp", /* load local pointer */ \
87 /* 2X */ "pfix", /* prefix */ \
88 /* 3X */ "ldnl", /* load non-local */ \
89 /* 4X */ "ldc", /* load constant */ \
90 /* 5X */ "ldnlp", /* load non-local pointer */ \
91 /* 6X */ "nfix", /* negative prefix */ \
92 /* 7X */ "ldl", /* load local */ \
93 /* 8X */ "adc", /* add constant */ \
94 /* 9X */ "call", /* call subroutine */ \
95 /* AX */ "cj", /* conditional jump */ \
96 /* BX */ "ajw", /* adjust workspace */ \
97 /* CX */ "eqc", /* equals constant */ \
98 /* DX */ "stl", /* store local */ \
99 /* EX */ "stnl", /* store non-local */ \
100 /* FX */ "opr" /* operate */ }
101
102 #define T_OPC_J 0
103 #define T_OPC_LDLP 1
104 #define T_OPC_PFIX 2
105 #define T_OPC_LDNL 3
106 #define T_OPC_LDC 4
107 #define T_OPC_LDNLP 5
108 #define T_OPC_NFIX 6
109 #define T_OPC_LDL 7
110 #define T_OPC_ADC 8
111 #define T_OPC_CALL 9
112 #define T_OPC_CJ 10
113 #define T_OPC_AJW 11
114 #define T_OPC_EQC 12
115 #define T_OPC_STL 13
116 #define T_OPC_STNL 14
117 #define T_OPC_OPR 15
118
119 /* Indirect ("operate") opcodes: */
120 #define N_TRANSPUTER_OPC_F_NAMES 0x90
121 #define TRANSPUTER_OPC_F_NAMES { \
122 "rev", "lb", "bsub", "endp", "diff", "add", "gcall","in", \
123 "prod", "gt", "wsub", "out", "sub", "startp","outbyte","outword",\
124 "seterr","0x11","resetch","csub0", "0x14", "stopp","ladd", "stlb", \
125 "sthf", "norm", "ldiv", "ldpi", "stlf", "xdble","ldpri","rem", \
126 "ret", "lend", "ldtimer","0x23","0x24","0x25", "0x26", "0x27", \
127 "0x28", "testerr","testpranal","tin", "div", "0x2d", "dist", "disc", \
128 "diss", "lmul", "not", "xor", "bcnt", "lshr", "lshl", "lsum", \
129 "lsub", "runp", "xword","sb", "gajw", "savel","saveh","wcnt", \
130 "shr" , "shl", "mint", "alt", "altwt","altend","and","enbt", \
131 "enbc", "enbs", "move", "or", "csngl", "ccnt1", "talt", "ldiff", \
132 "sthb", "taltwt","sum", "mul","sttimer","stoperr","cword","clrhalterr",\
133 "sethalterr", "testhalterr", "dup", "move2dinit", \
134 "move2dall", "move2dnonzero","move2dzero","0x5f", \
135 "0x60", "0x61", "0x62", "unpacksn","0x64","0x65","0x66","0x67", \
136 "0x68", "0x69", "0x6a", "0x6b", "postnormsn","roundsn","0x6e","0x6f", \
137 "0x70", "ldinf","fmul", "cflerr", \
138 "crcword", "crcbyte", "bitcnt", "bitrevword", \
139 "bitrevnbits","0x79","0x7a","0x7b", "0x7c", "0x7d", "0x7e", "0x7f", \
140 "0x80", "wsubdb","0x82", "0x83", "0x84", "0x85", "0x86", "0x87", \
141 "0x88", "0x89", "0x8a", "0x8b", "0x8c", "0x8d", "0x8e", "0x8f" }
142
143 #define T_OPC_F_REV 0x00
144 #define T_OPC_F_LB 0x01
145 #define T_OPC_F_BSUB 0x02
146 #define T_OPC_F_ENDP 0x03
147 #define T_OPC_F_DIFF 0x04
148 #define T_OPC_F_ADD 0x05
149 #define T_OPC_F_GCALL 0x06
150 #define T_OPC_F_IN 0x07
151 #define T_OPC_F_PROD 0x08
152 #define T_OPC_F_GT 0x09
153 #define T_OPC_F_WSUB 0x0a
154 #define T_OPC_F_OUT 0x0b
155 #define T_OPC_F_SUB 0x0c
156 #define T_OPC_F_STARTP 0x0d
157 #define T_OPC_F_OUTBYTE 0x0e
158 #define T_OPC_F_OUTWORD 0x0f
159 #define T_OPC_F_SETERR 0x10
160 #define T_OPC_F_RESETCH 0x12
161 #define T_OPC_F_CSUB0 0x13
162 #define T_OPC_F_STOPP 0x15
163 #define T_OPC_F_LADD 0x16
164 #define T_OPC_F_STLB 0x17
165 #define T_OPC_F_STHF 0x18
166 #define T_OPC_F_NORM 0x19
167 #define T_OPC_F_LDIV 0x1a
168 #define T_OPC_F_LDPI 0x1b
169 #define T_OPC_F_STLF 0x1c
170 #define T_OPC_F_XDBLE 0x1d
171 #define T_OPC_F_LDPRI 0x1e
172 #define T_OPC_F_REM 0x1f
173 #define T_OPC_F_RET 0x20
174 #define T_OPC_F_LEND 0x21
175 #define T_OPC_F_LDTIMER 0x22
176 #define T_OPC_F_TESTERR 0x29
177 #define T_OPC_F_TESTPRANAL 0x2a
178 #define T_OPC_F_TIN 0x2b
179 #define T_OPC_F_DIV 0x2c
180 #define T_OPC_F_DIST 0x2e
181 #define T_OPC_F_DISC 0x2f
182 #define T_OPC_F_DISS 0x30
183 #define T_OPC_F_LMUL 0x31
184 #define T_OPC_F_NOT 0x32
185 #define T_OPC_F_XOR 0x33
186 #define T_OPC_F_BCNT 0x34
187 #define T_OPC_F_LSHR 0x35
188 #define T_OPC_F_LSHL 0x36
189 #define T_OPC_F_LSUM 0x37
190 #define T_OPC_F_LSUB 0x38
191 #define T_OPC_F_RUNP 0x39
192 #define T_OPC_F_XWORD 0x3a
193 #define T_OPC_F_SB 0x3b
194 #define T_OPC_F_GAJW 0x3c
195 #define T_OPC_F_SAVEL 0x3d
196 #define T_OPC_F_SAVEH 0x3e
197 #define T_OPC_F_WCNT 0x3f
198 #define T_OPC_F_SHR 0x40
199 #define T_OPC_F_SHL 0x41
200 #define T_OPC_F_MINT 0x42
201 #define T_OPC_F_ALT 0x43
202 #define T_OPC_F_ALTWT 0x44
203 #define T_OPC_F_ALTEND 0x45
204 #define T_OPC_F_AND 0x46
205 #define T_OPC_F_ENBT 0x47
206 #define T_OPC_F_ENBC 0x48
207 #define T_OPC_F_ENBS 0x49
208 #define T_OPC_F_MOVE 0x4a
209 #define T_OPC_F_OR 0x4b
210 #define T_OPC_F_CSNGL 0x4c
211 #define T_OPC_F_CCNT1 0x4d
212 #define T_OPC_F_TALT 0x4e
213 #define T_OPC_F_LDIFF 0x4f
214 #define T_OPC_F_STHB 0x50
215 #define T_OPC_F_TALTWT 0x51
216 #define T_OPC_F_SUM 0x52
217 #define T_OPC_F_STTIMER 0x54
218 #define T_OPC_F_MUL 0x53
219 #define T_OPC_F_STOPERR 0x55
220 #define T_OPC_F_CWORD 0x56
221 #define T_OPC_F_CLRHALTERR 0x57
222 #define T_OPC_F_SETHALTERR 0x58
223 #define T_OPC_F_TESTHALTERR 0x59
224 #define T_OPC_F_DUP 0x5a
225 #define T_OPC_F_MOVE2DINIT 0x5b
226 #define T_OPC_F_MOVE2DALL 0x5c
227 #define T_OPC_F_MOVE2DNONZERO 0x5d
228 #define T_OPC_F_MOVE2DZERO 0x5e
229 #define T_OPC_F_UNPACKSN 0x63
230 #define T_OPC_F_POSTNORMSN 0x6c
231 #define T_OPC_F_ROUNDSN 0x6d
232 #define T_OPC_F_LDINF 0x71
233 #define T_OPC_F_FMUL 0x72
234 #define T_OPC_F_CFLERR 0x73
235 #define T_OPC_F_CRCWORD 0x74
236 #define T_OPC_F_CRCBYTE 0x75
237 #define T_OPC_F_BITCNT 0x76
238 #define T_OPC_F_BITREVWORD 0x77
239 #define T_OPC_F_BITREVNBITS 0x78
240 #define T_OPC_F_WSUBSB 0x81
241
242 #define TRANSPUTER_N_IC_ARGS 1
243 #define TRANSPUTER_INSTR_ALIGNMENT_SHIFT 0
244 #define TRANSPUTER_IC_ENTRIES_SHIFT 12
245 #define TRANSPUTER_IC_ENTRIES_PER_PAGE (1 << TRANSPUTER_IC_ENTRIES_SHIFT)
246 #define TRANSPUTER_PC_TO_IC_ENTRY(a) (((a)>>TRANSPUTER_INSTR_ALIGNMENT_SHIFT) \
247 & (TRANSPUTER_IC_ENTRIES_PER_PAGE-1))
248 #define TRANSPUTER_ADDR_TO_PAGENR(a) ((a) >> (TRANSPUTER_IC_ENTRIES_SHIFT \
249 + TRANSPUTER_INSTR_ALIGNMENT_SHIFT))
250
251 DYNTRANS_MISC_DECLARATIONS(transputer,TRANSPUTER,uint32_t)
252
253 #define TRANSPUTER_MAX_VPH_TLB_ENTRIES 128
254
255
256 struct transputer_cpu {
257 struct transputer_cpu_type_def cpu_type;
258
259 uint32_t a, b, c; /* GPRs */
260 uint32_t wptr; /* Workspace/stack pointer */
261 uint32_t oreg; /* Operand register */
262
263 uint64_t fa, fb, fc; /* Floating point registers */
264
265 int error; /* Error flags... */
266 int halt_on_error;
267 int fp_error;
268
269 uint32_t bptrreg0; /* High Priority Front Pointer */
270 uint32_t fptrreg0; /* High Priority Back Pointer */
271 uint32_t fptrreg1; /* Low Priority Front Pointer */
272 uint32_t bptrreg1; /* Low Priority Back Pointer */
273
274 /*
275 * Instruction translation cache and 32-bit virtual -> physical ->
276 * host address translation:
277 */
278 DYNTRANS_ITC(transputer)
279 VPH_TLBS(transputer,TRANSPUTER)
280 VPH32(transputer,TRANSPUTER,uint32_t,uint8_t)
281 };
282
283
284 /* cpu_transputer.c: */
285 int transputer_run_instr(struct cpu *cpu);
286 void transputer_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
287 unsigned char *host_page, int writeflag, uint64_t paddr_page);
288 void transputer_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
289 void transputer_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
290 int transputer_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
291 unsigned char *data, size_t len, int writeflag, int cache_flags);
292 int transputer_cpu_family_init(struct cpu_family *);
293
294
295 #endif /* CPU_TRANSPUTER_H */
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