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#ifndef CPU_SPARC_H |
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#define CPU_SPARC_H |
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|
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/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_sparc.h,v 1.41 2006/07/23 12:40:24 debug Exp $ |
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*/ |
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|
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#include "misc.h" |
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|
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|
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struct cpu_family; |
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|
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|
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/* SPARC CPU types: */ |
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struct sparc_cpu_type_def { |
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char *name; |
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int v; /* v8, v9 etc */ |
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int bits; /* 32 or 64 */ |
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int nwindows; /* usually 8 or more */ |
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int icache_shift; |
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int ilinesize; |
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int iway; |
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int dcache_shift; |
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int dlinesize; |
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int dway; |
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int l2cache_shift; |
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int l2linesize; |
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int l2way; |
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}; |
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|
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/* NOTE/TODO: Maybe some of the types listed below as v8 are in |
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fact v7; I haven't had time to check. Also, the nwindows value is |
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just bogus. */ |
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/* See http://www.sparc.com/standards/v8v9-numbers.html for |
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implementation numbers! */ |
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|
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#define SPARC_CPU_TYPE_DEFS { \ |
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{ "TMS390Z50", 8, 32, 8, 14,5,2, 14,5,2, 0,0,0 }, \ |
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{ "MB86904", 8, 32, 8, 14,5,2, 13,4,2, 0,0,0 }, \ |
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{ "MB86907", 8, 32, 8, 14,5,2, 14,5,2, 19,5,1 }, \ |
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{ "UltraSPARC", 9, 64, 8, 14,5,4, 14,5,4, 19,6,1 }, \ |
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{ "UltraSPARC-IIi", 9, 64, 8, 15,5,2, 14,5,2, 21,6,1 }, \ |
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{ "UltraSPARC-II", 9, 64, 8, 15,5,2, 14,5,2, 22,6,1 }, \ |
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{ NULL, 0, 0, 0, 0,0,0, 0,0,0, 0,0,0 } \ |
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} |
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|
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|
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#define SPARC_N_IC_ARGS 3 |
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#define SPARC_INSTR_ALIGNMENT_SHIFT 2 |
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#define SPARC_IC_ENTRIES_SHIFT 10 |
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#define SPARC_IC_ENTRIES_PER_PAGE (1 << SPARC_IC_ENTRIES_SHIFT) |
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#define SPARC_PC_TO_IC_ENTRY(a) (((a)>>SPARC_INSTR_ALIGNMENT_SHIFT) \ |
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& (SPARC_IC_ENTRIES_PER_PAGE-1)) |
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#define SPARC_ADDR_TO_PAGENR(a) ((a) >> (SPARC_IC_ENTRIES_SHIFT \ |
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+ SPARC_INSTR_ALIGNMENT_SHIFT)) |
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|
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#define SPARC_L2N 17 |
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#define SPARC_L3N 18 /* 4KB pages on 32-bit sparc, */ |
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/* 8KB pages on 64-bit? TODO */ |
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|
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DYNTRANS_MISC_DECLARATIONS(sparc,SPARC,uint64_t) |
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DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC,uint8_t) |
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|
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#define SPARC_MAX_VPH_TLB_ENTRIES 128 |
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|
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|
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#define N_SPARC_REG 32 |
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#define N_SPARC_INOUT_REG 8 |
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#define N_SPARC_LOCAL_REG 8 |
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#define SPARC_REG_NAMES { \ |
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"g0","g1","g2","g3","g4","g5","g6","g7", \ |
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"o0","o1","o2","o3","o4","o5","sp","o7", \ |
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"l0","l1","l2","l3","l4","l5","l6","l7", \ |
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"i0","i1","i2","i3","i4","i5","fp","i7" } |
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|
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#define SPARC_ZEROREG 0 /* g0 */ |
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#define SPARC_REG_G0 0 |
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#define SPARC_REG_G1 1 |
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#define SPARC_REG_G2 2 |
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#define SPARC_REG_G3 3 |
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#define SPARC_REG_G4 4 |
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#define SPARC_REG_G5 5 |
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#define SPARC_REG_G6 6 |
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#define SPARC_REG_G7 7 |
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#define SPARC_REG_O0 8 |
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#define SPARC_REG_O1 9 |
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#define SPARC_REG_O2 10 |
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#define SPARC_REG_O3 11 |
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#define SPARC_REG_O4 12 |
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#define SPARC_REG_O5 13 |
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#define SPARC_REG_O6 14 |
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#define SPARC_REG_O7 15 |
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#define SPARC_REG_L0 16 |
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#define SPARC_REG_L1 17 |
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#define SPARC_REG_L2 18 |
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#define SPARC_REG_L3 19 |
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#define SPARC_REG_L4 20 |
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#define SPARC_REG_L5 21 |
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#define SPARC_REG_L6 22 |
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#define SPARC_REG_L7 23 |
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#define SPARC_REG_I0 24 |
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#define SPARC_REG_I1 25 |
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#define SPARC_REG_I2 26 |
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#define SPARC_REG_I3 27 |
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#define SPARC_REG_I4 28 |
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#define SPARC_REG_I5 29 |
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#define SPARC_REG_I6 30 |
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#define SPARC_REG_I7 31 |
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|
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/* Privileged registers: */ |
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#define N_SPARC_PREG 32 |
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#define SPARC_PREG_NAMES { \ |
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"tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", \ |
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"pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", \ |
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"wstate", "fq", "reserved16", "reserved17", "reserved18", \ |
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"reserved19", "reserved20", "reserved21", "reserved22", \ |
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"reserved23", "reserved24", "reserved25", "reserved26", \ |
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"reserved27", "reserved28", "reserved29", "reserved30", \ |
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"ver" } |
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|
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#define N_SPARC_BRANCH_TYPES 16 |
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#define SPARC_BRANCH_NAMES { \ |
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"bn", "be", "ble", "bl", "bleu", "bcs", "bneg", "bvs", \ |
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"ba", "bne", "bg", "bge", "bgu", "bcc", "bpos", "bvc" } |
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|
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#define N_SPARC_REGBRANCH_TYPES 8 |
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#define SPARC_REGBRANCH_NAMES { \ |
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"br?","brz","brlez","brlz","br??","brnz", "brgz", "brgez" } |
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|
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#define N_ALU_INSTR_TYPES 64 |
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#define SPARC_ALU_NAMES { \ |
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"add", "and", "or", "xor", "sub", "andn", "orn", "xnor", \ |
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"addx", "[9]", "umul", "smul", "subx", "[13]", "udiv", "sdiv", \ |
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"addcc","andcc","orcc","xorcc","subcc","andncc","orncc","xnorcc",\ |
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"addxcc","[25]","umulcc","smulcc","subxcc","[29]","udivcc","sdivcc",\ |
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"taddcc","tsubcc","taddcctv","tsubcctv","mulscc","sll","srl","sra",\ |
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"rd" /* membar/stbar on sparcv9 */, \ |
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"rd" /* rd psr on pre-sparcv9 */, "rdpr","rd", \ |
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"[44]","[45]","popc","movre", \ |
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"wr*","saved/restored","wrpr","[51]", "[52]","[53]","[54]","[55]",\ |
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"jmpl", "rett", "trap", "flush", "save", "restore", "[62]","[63]" } |
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|
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#define N_LOADSTORE_TYPES 64 |
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#define SPARC_LOADSTORE_NAMES { \ |
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"lduw","ldub","lduh","ldd", "st","stb","sth","std", \ |
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"ldsw","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap", \ |
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"lda","lduba","lduha","ldda", "sta","stba","stha","stda", \ |
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"[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa", \ |
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"ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf", \ |
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"[40]","[41]","[42]","[43]", "[44]","prefetch","[46]","[47]", \ |
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"ldc","ldcsr","[50]","lddc", "stc","stcsr","scdfq","scdf", \ |
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"[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" } |
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|
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|
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/* Max number of Trap Levels and Windows: */ |
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#define MAXTL 4 |
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#define MAXWIN 32 |
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|
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|
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struct sparc_cpu { |
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struct sparc_cpu_type_def cpu_type; |
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|
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/* Registers in the Current Window: */ |
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uint64_t r[N_SPARC_REG]; |
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|
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uint64_t r_inout[MAXWIN][N_SPARC_INOUT_REG]; |
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uint64_t r_local[MAXWIN][N_SPARC_LOCAL_REG]; |
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|
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uint64_t scratch; |
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|
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/* Pre-SPARCv9 specific: */ |
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uint32_t psr; /* Processor State Register */ |
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uint32_t tbr; /* Trap base register */ |
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uint32_t wim; /* Window invalid mask */ |
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|
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/* SPARCv9 etc.: */ |
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uint64_t pstate; /* Processor State Register */ |
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uint64_t y; /* Y-reg (only low 32-bits used) */ |
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uint64_t fprs; /* Floating Point Register Status */ |
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uint64_t tick; /* Tick Register */ |
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uint64_t tick_cmpr; /* Tick Compare Register (?) */ |
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uint64_t ver; /* Version register */ |
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|
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uint8_t cwp; /* Current Window Pointer */ |
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uint8_t cansave; /* CANSAVE register */ |
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uint8_t canrestore; /* CANRESTORE register */ |
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uint8_t otherwin; /* OTHERWIN register */ |
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uint8_t cleanwin; /* CLEANWIN register */ |
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|
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uint8_t wstate; /* Window state */ |
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|
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uint8_t ccr; /* Condition Code Register */ |
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uint8_t asi; /* Address Space Identifier */ |
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uint8_t tl; /* Trap Level Register */ |
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uint8_t pil; /* Processor Interrupt Level Reg. */ |
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|
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uint64_t tpc[MAXTL]; /* Trap Program Counter */ |
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uint64_t tnpc[MAXTL]; /* Trap Next Program Counter */ |
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uint64_t tstate[MAXTL]; /* Trap State */ |
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uint32_t ttype[MAXTL]; /* Trap Type */ |
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|
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uint64_t tba; /* Trap Base Address */ |
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|
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/* |
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* Instruction translation cache and Virtual->Physical->Host |
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* address translation: |
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*/ |
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DYNTRANS_ITC(sparc) |
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VPH_TLBS(sparc,SPARC) |
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VPH32(sparc,SPARC,uint64_t,uint8_t) |
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VPH64(sparc,SPARC,uint8_t) |
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}; |
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|
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|
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/* Processor State Register (PSTATE) bit definitions: */ |
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#define SPARC_PSTATE_PID1 0x800 |
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#define SPARC_PSTATE_PID0 0x400 |
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#define SPARC_PSTATE_CLE 0x200 /* Current Little Endian */ |
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#define SPARC_PSTATE_TLE 0x100 /* Trap Little Endian */ |
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#define SPARC_PSTATE_MM_MASK 0x0c0 /* Memory Model (TODO) */ |
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#define SPARC_PSTATE_MM_SHIFT 6 |
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#define SPARC_PSTATE_RED 0x020 /* Reset/Error/Debug state */ |
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#define SPARC_PSTATE_PEF 0x010 /* Enable Floating-point */ |
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#define SPARC_PSTATE_AM 0x008 /* Address Mask */ |
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#define SPARC_PSTATE_PRIV 0x004 /* Privileged Mode */ |
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#define SPARC_PSTATE_IE 0x002 /* Interrupt Enable */ |
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#define SPARC_PSTATE_AG 0x001 /* Alternate Globals */ |
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|
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|
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/* Condition Code Register bit definitions: */ |
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#define SPARC_CCR_XCC_MASK 0xf0 |
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#define SPARC_CCR_XCC_SHIFT 4 |
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#define SPARC_CCR_ICC_MASK 0x0f |
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#define SPARC_CCR_N 8 |
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#define SPARC_CCR_Z 4 |
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#define SPARC_CCR_V 2 |
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#define SPARC_CCR_C 1 |
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|
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|
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/* CWP, CANSAVE, CANRESTORE, OTHERWIN, CLEANWIN bitmask: */ |
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#define SPARC_CWP_MASK 0x1f |
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|
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|
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/* Window State bit definitions: */ |
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#define SPARC_WSTATE_OTHER_MASK 0x38 |
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#define SPARC_WSTATE_OTHER_SHIFT 3 |
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#define SPARC_WSTATE_NORMAL_MASK 0x07 |
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|
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|
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/* Tick Register bit definitions: */ |
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#define SPARC_TICK_NPT (1ULL << 63) /* Non-privileged trap */ |
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|
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|
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/* Addess Space Identifier bit definitions: */ |
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#define SPARC_ASI_RESTRICTED 0x80 |
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|
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|
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/* Trap Level Register bit definitions: */ |
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#define SPARC_TL_MASK 0x07 |
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|
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|
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/* Processor Interrupt Level Register bit definitions: */ |
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#define SPARC_PIL_MASK 0x0f |
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|
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|
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/* Trap Type Register bit definitions: */ |
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#define SPARC_TTYPE_MASK 0x1ff |
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|
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|
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/* Trap Base Address bit definitions: */ |
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#define SPARC_TBA_MASK 0xffffffffffff8000ULL |
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|
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|
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/* |
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* Full address for a trap is: |
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* TBA<bits 63..15> || X || TTYPE[TL] || 00000 |
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* |
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* where X is a bit which is true if TL>0 when the trap was taken. |
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*/ |
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|
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|
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/* Version Register bit definitions: */ |
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#define SPARC_VER_MANUF_SHIFT 48 |
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#define SPARC_VER_IMPL_SHIFT 32 |
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#define SPARC_VER_MASK_SHIFT 24 |
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#define SPARC_VER_MAXTL_SHIFT 8 |
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#define SPARC_VER_MAXWIN_SHIFT 0 |
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|
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|
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/* cpu_sparc.c: */ |
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int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
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int sparc_run_instr(struct cpu *cpu); |
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void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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int sparc32_run_instr(struct cpu *cpu); |
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void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void sparc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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void sparc_init_64bit_dummy_tables(struct cpu *cpu); |
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int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int sparc_cpu_family_init(struct cpu_family *); |
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|
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|
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#endif /* CPU_SPARC_H */ |
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