/[gxemul]/trunk/src/include/cpu_sparc.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/include/cpu_sparc.h

Parent Directory Parent Directory | Revision Log Revision Log


Revision 44 - (show annotations)
Mon Oct 8 16:22:56 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 12369 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1632 2007/09/11 21:46:35 debug Exp $
20070616	Implementing the MIPS32/64 revision 2 "ror" instruction.
20070617	Adding a struct for each physpage which keeps track of which
		ranges within that page (base offset, length) that are
		continuously translatable. When running with native code
		generation enabled (-b), a range is added after each read-
		ahead loop.
		Experimenting with using the physical program counter sample
		data (implemented 20070608) together with the "translatable
		range" information, to figure out which physical address ranges
		would be worth translating to native code (if the number of
		samples falling within a range is above a certain threshold).
20070618	Adding automagic building of .index comment files for
		src/file/, src/promemul/, src src/useremul/ as well.
		Adding a "has been translated" bit to the ranges, so that only
		not-yet-translated ranges will be sampled.
20070619	Moving src/cpu.c and src/memory_rw.c into src/cpus/,
		src/device.c into src/devices/, and src/machine.c into
		src/machines/.
		Creating a skeleton cc/ld native backend module; beginning on
		the function which will detect cc command line, etc.
20070620	Continuing on the native code generation infrastructure.
20070621	Moving src/x11.c and src/console.c into a new src/console/
		subdir (for everything that is console or framebuffer related).
		Moving src/symbol*.c into a new src/symbol/, which should
		contain anything that is symbol handling related.
20070624	Making the program counter sampling threshold a "settings
		variable" (sampling_threshold), i.e. it can now be changed
		during runtime.
		Switching the RELEASE notes format from plain text to HTML.
		If the TMPDIR environment variable is set, it is used instead
		of "/tmp" for temporary files.
		Continuing on the cc/ld backend: simple .c code is generated,
		the compiler and linker are called, etc.
		Adding detection of host architecture to the configure script
		(again), and adding icache invalidation support (only
		implemented for Alpha hosts so far).
20070625	Simplifying the program counter sampling mechanism.
20070626	Removing the cc/ld native code generation stuff, program
		counter sampling, etc; it would not have worked well in the
		general case.
20070627	Removing everything related to native code generation.
20070629	Removing the (practically unusable) support for multiple
		emulations. (The single emulation allowed now still supports
		multiple simultaneous machines, as before.)
		Beginning on PCCTWO and M88K interrupts.
20070723	Adding a dummy skeleton for emulation of M32R processors.
20070901	Fixing a warning found by "gcc version 4.3.0 20070817
		(experimental)" on amd64.
20070905	Removing some more traces of the old "multiple emulations"
		code.
		Also looking in /usr/local/include and /usr/local/lib for
		X11 libs, when running configure.
20070909	Minor updates to the guest OS install instructions, in
		preparation for the NetBSD 4.0 release.
20070918	More testing of NetBSD 4.0 RC1.

1 #ifndef CPU_SPARC_H
2 #define CPU_SPARC_H
3
4 /*
5 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_sparc.h,v 1.49 2007/07/20 09:03:33 debug Exp $
32 */
33
34 #include "misc.h"
35
36
37 struct cpu_family;
38
39
40 /* SPARC CPU types: */
41 struct sparc_cpu_type_def {
42 char *name;
43 int v; /* v8, v9 etc */
44 int h; /* hypervisor? sun4v = 1 */
45 int bits; /* 32 or 64 */
46 int nwindows; /* usually 8 or more */
47 int icache_shift;
48 int ilinesize;
49 int iway;
50 int dcache_shift;
51 int dlinesize;
52 int dway;
53 int l2cache_shift;
54 int l2linesize;
55 int l2way;
56 };
57
58 /* NOTE/TODO: Maybe some of the types listed below as v8 are in
59 fact v7; I haven't had time to check. Also, the nwindows value is
60 just bogus. */
61 /* See http://www.sparc.com/standards/v8v9-numbers.html for
62 implementation numbers! */
63 /* Note/TODO: sun4v is listed as 10 */
64
65 #define SPARC_CPU_TYPE_DEFS { \
66 { "TMS390Z50", 8, 0, 32, 8, 14,5,2, 14,5,2, 0,0,0 }, \
67 { "MB86904", 8, 0, 32, 8, 14,5,2, 13,4,2, 0,0,0 }, \
68 { "MB86907", 8, 0, 32, 8, 14,5,2, 14,5,2, 19,5,1 }, \
69 { "UltraSPARC", 9, 0, 64, 8, 14,5,4, 14,5,4, 19,6,1 }, \
70 { "UltraSPARC-IIi", 9, 0, 64, 8, 15,5,2, 14,5,2, 21,6,1 }, \
71 { "UltraSPARC-II", 9, 0, 64, 8, 15,5,2, 14,5,2, 22,6,1 }, \
72 { "T1", 9, 1, 64, 8, 15,5,2, 14,5,2, 22,6,1 }, \
73 { NULL, 0, 0, 0, 0, 0,0,0, 0,0,0, 0,0,0 } \
74 }
75
76
77 #define SPARC_N_IC_ARGS 3
78 #define SPARC_INSTR_ALIGNMENT_SHIFT 2
79 #define SPARC_IC_ENTRIES_SHIFT 10
80 #define SPARC_IC_ENTRIES_PER_PAGE (1 << SPARC_IC_ENTRIES_SHIFT)
81 #define SPARC_PC_TO_IC_ENTRY(a) (((a)>>SPARC_INSTR_ALIGNMENT_SHIFT) \
82 & (SPARC_IC_ENTRIES_PER_PAGE-1))
83 #define SPARC_ADDR_TO_PAGENR(a) ((a) >> (SPARC_IC_ENTRIES_SHIFT \
84 + SPARC_INSTR_ALIGNMENT_SHIFT))
85
86 #define SPARC_L2N 17
87 #define SPARC_L3N 18 /* 4KB pages on 32-bit sparc, */
88 /* 8KB pages on 64-bit? TODO */
89
90 DYNTRANS_MISC_DECLARATIONS(sparc,SPARC,uint64_t)
91 DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC,uint8_t)
92
93 #define SPARC_MAX_VPH_TLB_ENTRIES 128
94
95
96 #define N_SPARC_REG 32
97 #define N_SPARC_GLOBAL_REG 8
98 #define N_SPARC_INOUT_REG 8
99 #define N_SPARC_LOCAL_REG 8
100 #define SPARC_REG_NAMES { \
101 "g0","g1","g2","g3","g4","g5","g6","g7", \
102 "o0","o1","o2","o3","o4","o5","sp","o7", \
103 "l0","l1","l2","l3","l4","l5","l6","l7", \
104 "i0","i1","i2","i3","i4","i5","fp","i7" }
105
106 #define SPARC_ZEROREG 0 /* g0 */
107 #define SPARC_REG_G0 0
108 #define SPARC_REG_G1 1
109 #define SPARC_REG_G2 2
110 #define SPARC_REG_G3 3
111 #define SPARC_REG_G4 4
112 #define SPARC_REG_G5 5
113 #define SPARC_REG_G6 6
114 #define SPARC_REG_G7 7
115 #define SPARC_REG_O0 8
116 #define SPARC_REG_O1 9
117 #define SPARC_REG_O2 10
118 #define SPARC_REG_O3 11
119 #define SPARC_REG_O4 12
120 #define SPARC_REG_O5 13
121 #define SPARC_REG_O6 14
122 #define SPARC_REG_O7 15
123 #define SPARC_REG_L0 16
124 #define SPARC_REG_L1 17
125 #define SPARC_REG_L2 18
126 #define SPARC_REG_L3 19
127 #define SPARC_REG_L4 20
128 #define SPARC_REG_L5 21
129 #define SPARC_REG_L6 22
130 #define SPARC_REG_L7 23
131 #define SPARC_REG_I0 24
132 #define SPARC_REG_I1 25
133 #define SPARC_REG_I2 26
134 #define SPARC_REG_I3 27
135 #define SPARC_REG_I4 28
136 #define SPARC_REG_I5 29
137 #define SPARC_REG_I6 30
138 #define SPARC_REG_I7 31
139
140 /* Privileged registers: */
141 #define N_SPARC_PREG 32
142 #define SPARC_PREG_NAMES { \
143 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", \
144 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", \
145 "wstate", "fq", "reserved16", "reserved17", "reserved18", \
146 "reserved19", "reserved20", "reserved21", "reserved22", \
147 "reserved23", "reserved24", "reserved25", "reserved26", \
148 "reserved27", "reserved28", "reserved29", "reserved30", \
149 "ver" }
150
151 #define N_SPARC_BRANCH_TYPES 16
152 #define SPARC_BRANCH_NAMES { \
153 "bn", "be", "ble", "bl", "bleu", "bcs", "bneg", "bvs", \
154 "ba", "bne", "bg", "bge", "bgu", "bcc", "bpos", "bvc" }
155
156 #define N_SPARC_REGBRANCH_TYPES 8
157 #define SPARC_REGBRANCH_NAMES { \
158 "br?","brz","brlez","brlz","br??","brnz", "brgz", "brgez" }
159
160 #define N_ALU_INSTR_TYPES 64
161 #define SPARC_ALU_NAMES { \
162 "add", "and", "or", "xor", "sub", "andn", "orn", "xnor", \
163 "addx", "[9]", "umul", "smul", "subx", "[13]", "udiv", "sdiv", \
164 "addcc","andcc","orcc","xorcc","subcc","andncc","orncc","xnorcc",\
165 "addxcc","[25]","umulcc","smulcc","subxcc","[29]","udivcc","sdivcc",\
166 "taddcc","tsubcc","taddcctv","tsubcctv","mulscc","sll","srl","sra",\
167 "rd" /* membar/stbar on sparcv9 */, \
168 "rd" /* rd psr on pre-sparcv9 */, "rdpr","rd", \
169 "[44]","[45]","popc","movre", \
170 "wr*","saved/restored","wrpr","[51]", "[52]","[53]","[54]","[55]",\
171 "jmpl", "rett", "trap", "flush", "save", "restore", "[62]","[63]" }
172
173 #define N_LOADSTORE_TYPES 64
174 #define SPARC_LOADSTORE_NAMES { \
175 "lduw","ldub","lduh","ldd", "st","stb","sth","std", \
176 "ldsw","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap", \
177 "lda","lduba","lduha","ldda", "sta","stba","stha","stda", \
178 "[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa", \
179 "ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf", \
180 "[40]","[41]","[42]","[43]", "[44]","prefetch","[46]","[47]", \
181 "ldc","ldcsr","[50]","lddc", "stc","stcsr","scdfq","scdf", \
182 "[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" }
183
184
185 /* Max number of Trap Levels, Global Levels, and Register Windows: */
186 #define MAXTL 6
187 #define MAXGL 7
188 #define N_REG_WINDOWS 8
189
190
191 struct sparc_cpu {
192 struct sparc_cpu_type_def cpu_type;
193
194 /* Registers in the Current Window: */
195 uint64_t r[N_SPARC_REG];
196
197 uint64_t r_inout[N_REG_WINDOWS][N_SPARC_INOUT_REG];
198 uint64_t r_local[N_REG_WINDOWS][N_SPARC_LOCAL_REG];
199
200 uint64_t r_global[MAXGL+1][N_SPARC_GLOBAL_REG];
201
202 uint64_t scratch;
203
204 /* Pre-SPARCv9 specific: */
205 uint32_t psr; /* Processor State Register */
206 uint32_t tbr; /* Trap base register */
207 uint32_t wim; /* Window invalid mask */
208
209 /* SPARCv9 etc.: */
210 uint64_t pstate; /* Processor State Register */
211 uint64_t y; /* Y-reg (only low 32-bits used) */
212 uint64_t fprs; /* Floating Point Register Status */
213 uint64_t tick; /* Tick Register */
214 uint64_t tick_cmpr; /* Tick Compare Register (?) */
215 uint64_t ver; /* Version register */
216
217 uint8_t cwp; /* Current Window Pointer */
218 uint8_t cansave; /* CANSAVE register */
219 uint8_t canrestore; /* CANRESTORE register */
220 uint8_t otherwin; /* OTHERWIN register */
221 uint8_t cleanwin; /* CLEANWIN register */
222
223 uint8_t wstate; /* Window state */
224
225 uint8_t ccr; /* Condition Code Register */
226 uint8_t asi; /* Address Space Identifier */
227 uint8_t tl; /* Trap Level Register */
228 uint8_t gl; /* Global Level Register */
229 uint8_t pil; /* Processor Interrupt Level Reg. */
230
231 uint64_t tpc[MAXTL]; /* Trap Program Counter */
232 uint64_t tnpc[MAXTL]; /* Trap Next Program Counter */
233 uint64_t tstate[MAXTL]; /* Trap State */
234 uint32_t ttype[MAXTL]; /* Trap Type */
235
236 uint64_t tba; /* Trap Base Address */
237
238 uint64_t hpstate; /* Hyper-Privileged State Register */
239 uint64_t htstate[MAXTL]; /* Hyper-Privileged Trap State */
240 uint64_t hintp; /* Hyper-Privileged InterruptPending */
241 uint64_t htba; /* Hyper-Privileged Trap Base Addr */
242 uint64_t hver; /* Hyper-Privileged Version Reg. */
243
244
245 /*
246 * Instruction translation cache and Virtual->Physical->Host
247 * address translation:
248 */
249 DYNTRANS_ITC(sparc)
250 VPH_TLBS(sparc,SPARC)
251 VPH32(sparc,SPARC)
252 VPH64(sparc,SPARC)
253 };
254
255
256 /* Processor State Register (PSTATE) bit definitions: */
257 #define SPARC_PSTATE_PID1 0x800
258 #define SPARC_PSTATE_PID0 0x400
259 #define SPARC_PSTATE_CLE 0x200 /* Current Little Endian */
260 #define SPARC_PSTATE_TLE 0x100 /* Trap Little Endian */
261 #define SPARC_PSTATE_MM_MASK 0x0c0 /* Memory Model (TODO) */
262 #define SPARC_PSTATE_MM_SHIFT 6
263 #define SPARC_PSTATE_RED 0x020 /* Reset/Error/Debug state */
264 #define SPARC_PSTATE_PEF 0x010 /* Enable Floating-point */
265 #define SPARC_PSTATE_AM 0x008 /* Address Mask */
266 #define SPARC_PSTATE_PRIV 0x004 /* Privileged Mode */
267 #define SPARC_PSTATE_IE 0x002 /* Interrupt Enable */
268 #define SPARC_PSTATE_AG 0x001 /* Alternate Globals */
269
270
271 /* Hyper-Privileged State Register (HPSTATE) bit definitions: */
272 #define SPARC_HPSTATE_ID 0x800
273 #define SPARC_HPSTATE_IBE 0x400 /* Instruction Break Enable */
274 #define SPARC_HPSTATE_RED 0x020 /* Reset/Error/Debug state */
275 #define SPARC_HPSTATE_HPRIV 0x004 /* Hyper-Privileged mode */
276 #define SPARC_HPSTATE_TLZ 0x001 /* Trap Level Zero trap enable */
277
278
279 /* Condition Code Register bit definitions: */
280 #define SPARC_CCR_XCC_MASK 0xf0
281 #define SPARC_CCR_XCC_SHIFT 4
282 #define SPARC_CCR_ICC_MASK 0x0f
283 #define SPARC_CCR_N 8
284 #define SPARC_CCR_Z 4
285 #define SPARC_CCR_V 2
286 #define SPARC_CCR_C 1
287
288
289 /* CWP, CANSAVE, CANRESTORE, OTHERWIN, CLEANWIN bitmask: */
290 #define SPARC_CWP_MASK 0x1f
291
292
293 /* Window State bit definitions: */
294 #define SPARC_WSTATE_OTHER_MASK 0x38
295 #define SPARC_WSTATE_OTHER_SHIFT 3
296 #define SPARC_WSTATE_NORMAL_MASK 0x07
297
298
299 /* Tick Register bit definitions: */
300 #define SPARC_TICK_NPT (1ULL << 63) /* Non-privileged trap */
301
302
303 /* Addess Space Identifier bit definitions: */
304 #define SPARC_ASI_RESTRICTED 0x80
305
306
307 /* Trap Level Register bit definitions: */
308 #define SPARC_TL_MASK 0x07
309
310
311 /* Processor Interrupt Level Register bit definitions: */
312 #define SPARC_PIL_MASK 0x0f
313
314
315 /* Trap Type Register bit definitions: */
316 #define SPARC_TTYPE_MASK 0x1ff
317
318
319 /* Trap Base Address bit definitions: */
320 #define SPARC_TBA_MASK 0xffffffffffff8000ULL
321
322
323 /*
324 * Full address for a trap is:
325 * TBA<bits 63..15> || X || TTYPE[TL] || 00000
326 *
327 * where X is a bit which is true if TL>0 when the trap was taken.
328 */
329
330
331 /* Version Register bit definitions: */
332 #define SPARC_VER_MANUF_SHIFT 48
333 #define SPARC_VER_IMPL_SHIFT 32
334 #define SPARC_VER_MASK_SHIFT 24
335 #define SPARC_VER_MAXTL_SHIFT 8
336 #define SPARC_VER_MAXWIN_SHIFT 0
337
338
339 /* cpu_sparc.c: */
340 int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
341 int sparc_run_instr(struct cpu *cpu);
342 void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
343 unsigned char *host_page, int writeflag, uint64_t paddr_page);
344 void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
345 void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
346 int sparc32_run_instr(struct cpu *cpu);
347 void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
348 unsigned char *host_page, int writeflag, uint64_t paddr_page);
349 void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
350 void sparc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
351 void sparc_init_64bit_dummy_tables(struct cpu *cpu);
352 int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
353 unsigned char *data, size_t len, int writeflag, int cache_flags);
354 int sparc_cpu_family_init(struct cpu_family *);
355
356 /* memory_sparc.c: */
357 int sparc_translate_v2p(struct cpu *cpu, uint64_t vaddr,
358 uint64_t *return_addr, int flags);
359
360
361 #endif /* CPU_SPARC_H */

  ViewVC Help
Powered by ViewVC 1.1.26