/[gxemul]/trunk/src/include/cpu_sparc.h
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revision 24 by dpavlin, Mon Oct 8 16:19:56 2007 UTC revision 28 by dpavlin, Mon Oct 8 16:20:26 2007 UTC
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_sparc.h,v 1.38 2006/05/18 05:10:44 debug Exp $   *  $Id: cpu_sparc.h,v 1.40 2006/07/16 13:32:28 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 40  struct cpu_family; Line 40  struct cpu_family;
40  /*  SPARC CPU types:  */  /*  SPARC CPU types:  */
41  struct sparc_cpu_type_def {  struct sparc_cpu_type_def {
42          char            *name;          char            *name;
43          int             bits;          int             v;                      /*  v8, v9 etc  */
44            int             bits;                   /*  32 or 64  */
45            int             nwindows;               /*  usually 8 or more  */
46          int             icache_shift;          int             icache_shift;
47          int             ilinesize;          int             ilinesize;
48          int             iway;          int             iway;
# Line 52  struct sparc_cpu_type_def { Line 54  struct sparc_cpu_type_def {
54          int             l2way;          int             l2way;
55  };  };
56    
57    /*  NOTE/TODO: Maybe some of the types listed below as v8 are in
58        fact v7; I haven't had time to check. Also, the nwindows value is
59        just bogus.  */
60    /*  See http://www.sparc.com/standards/v8v9-numbers.html for
61        implementation numbers!  */
62    
63  #define SPARC_CPU_TYPE_DEFS     {                                       \  #define SPARC_CPU_TYPE_DEFS     {                                       \
64          { "TMS390Z50",          32, 14,5,2, 14,5,2,  0,0,0 },           \          { "TMS390Z50",          8, 32, 8, 14,5,2, 14,5,2,  0,0,0 },     \
65          { "MB86904",            32, 14,5,2, 13,4,2,  0,0,0 },           \          { "MB86904",            8, 32, 8, 14,5,2, 13,4,2,  0,0,0 },     \
66          { "MB86907",            32, 14,5,2, 14,5,2, 19,5,1 },           \          { "MB86907",            8, 32, 8, 14,5,2, 14,5,2, 19,5,1 },     \
67          { "UltraSPARC",         64, 14,5,4, 14,5,4, 19,6,1 },           \          { "UltraSPARC",         9, 64, 8, 14,5,4, 14,5,4, 19,6,1 },     \
68          { "UltraSPARC-IIi",     64, 15,5,2, 14,5,2, 21,6,1 },           \          { "UltraSPARC-IIi",     9, 64, 8, 15,5,2, 14,5,2, 21,6,1 },     \
69          { "UltraSPARC-II",      64, 15,5,2, 14,5,2, 22,6,1 },           \          { "UltraSPARC-II",      9, 64, 8, 15,5,2, 14,5,2, 22,6,1 },     \
70          { NULL,                 0,  0,0,0,  0,0,0,   0,0,0 }            \          { NULL,                 0,  0, 0,  0,0,0,  0,0,0,  0,0,0 }      \
71          }          }
72    
73    
# Line 83  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC Line 91  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC
91    
92    
93  #define N_SPARC_REG             32  #define N_SPARC_REG             32
94    #define N_SPARC_INOUT_REG       8
95    #define N_SPARC_LOCAL_REG       8
96  #define SPARC_REG_NAMES {                               \  #define SPARC_REG_NAMES {                               \
97          "g0","g1","g2","g3","g4","g5","g6","g7",        \          "g0","g1","g2","g3","g4","g5","g6","g7",        \
98          "o0","o1","o2","o3","o4","o5","sp","o7",        \          "o0","o1","o2","o3","o4","o5","sp","o7",        \
# Line 158  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC Line 168  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC
168    
169  #define N_LOADSTORE_TYPES       64  #define N_LOADSTORE_TYPES       64
170  #define SPARC_LOADSTORE_NAMES {                                         \  #define SPARC_LOADSTORE_NAMES {                                         \
171          "ld","ldub","lduh","ldd", "st","stb","sth","std",               \          "lduw","ldub","lduh","ldd", "st","stb","sth","std",             \
172          "[8]","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap",        \          "ldsw","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap",       \
173          "lda","lduba","lduha","ldda", "sta","stba","stha","stda",       \          "lda","lduba","lduha","ldda", "sta","stba","stha","stda",       \
174          "[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa",  \          "[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa",  \
175          "ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf",      \          "ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf",      \
# Line 179  struct sparc_cpu { Line 189  struct sparc_cpu {
189          /*  Registers in the Current Window:  */          /*  Registers in the Current Window:  */
190          uint64_t        r[N_SPARC_REG];          uint64_t        r[N_SPARC_REG];
191    
192            uint64_t        r_inout[MAXWIN][N_SPARC_INOUT_REG];
193            uint64_t        r_local[MAXWIN][N_SPARC_LOCAL_REG];
194    
195          uint64_t        scratch;          uint64_t        scratch;
196    
197          /*  Pre-SPARCv9 specific:  */          /*  Pre-SPARCv9 specific:  */
# Line 302  struct sparc_cpu { Line 315  struct sparc_cpu {
315    
316  /*  cpu_sparc.c:  */  /*  cpu_sparc.c:  */
317  int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);  int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
318    int sparc_run_instr(struct cpu *cpu);
319  void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
320          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
321  void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
322  void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
323    int sparc32_run_instr(struct cpu *cpu);
324  void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
325          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
326  void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);

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