/[gxemul]/trunk/src/include/cpu_sparc.h
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revision 32 by dpavlin, Mon Oct 8 16:20:58 2007 UTC revision 36 by dpavlin, Mon Oct 8 16:21:34 2007 UTC
# Line 2  Line 2 
2  #define CPU_SPARC_H  #define CPU_SPARC_H
3    
4  /*  /*
5   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_sparc.h,v 1.42 2006/09/04 15:35:55 debug Exp $   *  $Id: cpu_sparc.h,v 1.46 2007/03/16 18:49:06 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 41  struct cpu_family; Line 41  struct cpu_family;
41  struct sparc_cpu_type_def {  struct sparc_cpu_type_def {
42          char            *name;          char            *name;
43          int             v;                      /*  v8, v9 etc  */          int             v;                      /*  v8, v9 etc  */
44            int             h;                      /*  hypervisor? sun4v = 1  */
45          int             bits;                   /*  32 or 64  */          int             bits;                   /*  32 or 64  */
46          int             nwindows;               /*  usually 8 or more  */          int             nwindows;               /*  usually 8 or more  */
47          int             icache_shift;          int             icache_shift;
# Line 59  struct sparc_cpu_type_def { Line 60  struct sparc_cpu_type_def {
60      just bogus.  */      just bogus.  */
61  /*  See http://www.sparc.com/standards/v8v9-numbers.html for  /*  See http://www.sparc.com/standards/v8v9-numbers.html for
62      implementation numbers!  */      implementation numbers!  */
63    /*  Note/TODO: sun4v is listed as 10  */
64    
65  #define SPARC_CPU_TYPE_DEFS     {                                       \  #define SPARC_CPU_TYPE_DEFS     {                                       \
66          { "TMS390Z50",          8, 32, 8, 14,5,2, 14,5,2,  0,0,0 },     \          { "TMS390Z50",          8, 0, 32, 8, 14,5,2, 14,5,2,  0,0,0 },  \
67          { "MB86904",            8, 32, 8, 14,5,2, 13,4,2,  0,0,0 },     \          { "MB86904",            8, 0, 32, 8, 14,5,2, 13,4,2,  0,0,0 },  \
68          { "MB86907",            8, 32, 8, 14,5,2, 14,5,2, 19,5,1 },     \          { "MB86907",            8, 0, 32, 8, 14,5,2, 14,5,2, 19,5,1 },  \
69          { "UltraSPARC",         9, 64, 8, 14,5,4, 14,5,4, 19,6,1 },     \          { "UltraSPARC",         9, 0, 64, 8, 14,5,4, 14,5,4, 19,6,1 },  \
70          { "UltraSPARC-IIi",     9, 64, 8, 15,5,2, 14,5,2, 21,6,1 },     \          { "UltraSPARC-IIi",     9, 0, 64, 8, 15,5,2, 14,5,2, 21,6,1 },  \
71          { "UltraSPARC-II",      9, 64, 8, 15,5,2, 14,5,2, 22,6,1 },     \          { "UltraSPARC-II",      9, 0, 64, 8, 15,5,2, 14,5,2, 22,6,1 },  \
72          { NULL,                 0,  0, 0,  0,0,0,  0,0,0,  0,0,0 }      \          { "T1",                 9, 1, 64, 8, 15,5,2, 14,5,2, 22,6,1 },  \
73            { NULL,                 0, 0,  0, 0,  0,0,0,  0,0,0,  0,0,0 }   \
74          }          }
75    
76    
# Line 91  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC Line 94  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC
94    
95    
96  #define N_SPARC_REG             32  #define N_SPARC_REG             32
97    #define N_SPARC_GLOBAL_REG      8
98  #define N_SPARC_INOUT_REG       8  #define N_SPARC_INOUT_REG       8
99  #define N_SPARC_LOCAL_REG       8  #define N_SPARC_LOCAL_REG       8
100  #define SPARC_REG_NAMES {                               \  #define SPARC_REG_NAMES {                               \
# Line 178  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC Line 182  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC
182          "[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" }          "[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" }
183    
184    
185  /*  Max number of Trap Levels and Windows:  */  /*  Max number of Trap Levels, Global Levels, and Register Windows:  */
186  #define MAXTL                   4  #define MAXTL                   6
187  #define MAXWIN                  32  #define MAXGL                   7
188    #define N_REG_WINDOWS           8
189    
190    
191  struct sparc_cpu {  struct sparc_cpu {
# Line 189  struct sparc_cpu { Line 194  struct sparc_cpu {
194          /*  Registers in the Current Window:  */          /*  Registers in the Current Window:  */
195          uint64_t        r[N_SPARC_REG];          uint64_t        r[N_SPARC_REG];
196    
197          uint64_t        r_inout[MAXWIN][N_SPARC_INOUT_REG];          uint64_t        r_inout[N_REG_WINDOWS][N_SPARC_INOUT_REG];
198          uint64_t        r_local[MAXWIN][N_SPARC_LOCAL_REG];          uint64_t        r_local[N_REG_WINDOWS][N_SPARC_LOCAL_REG];
199    
200            uint64_t        r_global[MAXGL+1][N_SPARC_GLOBAL_REG];
201    
202          uint64_t        scratch;          uint64_t        scratch;
203    
# Line 218  struct sparc_cpu { Line 225  struct sparc_cpu {
225          uint8_t         ccr;            /*  Condition Code Register  */          uint8_t         ccr;            /*  Condition Code Register  */
226          uint8_t         asi;            /*  Address Space Identifier  */          uint8_t         asi;            /*  Address Space Identifier  */
227          uint8_t         tl;             /*  Trap Level Register  */          uint8_t         tl;             /*  Trap Level Register  */
228            uint8_t         gl;             /*  Global Level Register  */
229          uint8_t         pil;            /*  Processor Interrupt Level Reg.  */          uint8_t         pil;            /*  Processor Interrupt Level Reg.  */
230    
231          uint64_t        tpc[MAXTL];     /*  Trap Program Counter  */          uint64_t        tpc[MAXTL];     /*  Trap Program Counter  */
# Line 227  struct sparc_cpu { Line 235  struct sparc_cpu {
235    
236          uint64_t        tba;            /*  Trap Base Address  */          uint64_t        tba;            /*  Trap Base Address  */
237    
238            uint64_t        hpstate;        /*  Hyper-Privileged State Register  */
239            uint64_t        htstate[MAXTL]; /*  Hyper-Privileged Trap State  */
240            uint64_t        hintp;          /*  Hyper-Privileged InterruptPending */
241            uint64_t        htba;           /*  Hyper-Privileged Trap Base Addr  */
242            uint64_t        hver;           /*  Hyper-Privileged Version Reg.  */
243    
244    
245          /*          /*
246           *  Instruction translation cache and Virtual->Physical->Host           *  Instruction translation cache and Virtual->Physical->Host
247           *  address translation:           *  address translation:
# Line 253  struct sparc_cpu { Line 268  struct sparc_cpu {
268  #define SPARC_PSTATE_AG         0x001   /*  Alternate Globals  */  #define SPARC_PSTATE_AG         0x001   /*  Alternate Globals  */
269    
270    
271    /*  Hyper-Privileged State Register (HPSTATE) bit definitions:  */
272    #define SPARC_HPSTATE_ID        0x800
273    #define SPARC_HPSTATE_IBE       0x400   /*  Instruction Break Enable  */
274    #define SPARC_HPSTATE_RED       0x020   /*  Reset/Error/Debug state  */
275    #define SPARC_HPSTATE_HPRIV     0x004   /*  Hyper-Privileged mode  */
276    #define SPARC_HPSTATE_TLZ       0x001   /*  Trap Level Zero trap enable  */
277    
278    
279  /*  Condition Code Register bit definitions:  */  /*  Condition Code Register bit definitions:  */
280  #define SPARC_CCR_XCC_MASK      0xf0  #define SPARC_CCR_XCC_MASK      0xf0
281  #define SPARC_CCR_XCC_SHIFT     4  #define SPARC_CCR_XCC_SHIFT     4
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