/[gxemul]/trunk/src/include/cpu_sparc.h
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revision 24 by dpavlin, Mon Oct 8 16:19:56 2007 UTC revision 36 by dpavlin, Mon Oct 8 16:21:34 2007 UTC
# Line 2  Line 2 
2  #define CPU_SPARC_H  #define CPU_SPARC_H
3    
4  /*  /*
5   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_sparc.h,v 1.38 2006/05/18 05:10:44 debug Exp $   *  $Id: cpu_sparc.h,v 1.46 2007/03/16 18:49:06 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 40  struct cpu_family; Line 40  struct cpu_family;
40  /*  SPARC CPU types:  */  /*  SPARC CPU types:  */
41  struct sparc_cpu_type_def {  struct sparc_cpu_type_def {
42          char            *name;          char            *name;
43          int             bits;          int             v;                      /*  v8, v9 etc  */
44            int             h;                      /*  hypervisor? sun4v = 1  */
45            int             bits;                   /*  32 or 64  */
46            int             nwindows;               /*  usually 8 or more  */
47          int             icache_shift;          int             icache_shift;
48          int             ilinesize;          int             ilinesize;
49          int             iway;          int             iway;
# Line 52  struct sparc_cpu_type_def { Line 55  struct sparc_cpu_type_def {
55          int             l2way;          int             l2way;
56  };  };
57    
58    /*  NOTE/TODO: Maybe some of the types listed below as v8 are in
59        fact v7; I haven't had time to check. Also, the nwindows value is
60        just bogus.  */
61    /*  See http://www.sparc.com/standards/v8v9-numbers.html for
62        implementation numbers!  */
63    /*  Note/TODO: sun4v is listed as 10  */
64    
65  #define SPARC_CPU_TYPE_DEFS     {                                       \  #define SPARC_CPU_TYPE_DEFS     {                                       \
66          { "TMS390Z50",          32, 14,5,2, 14,5,2,  0,0,0 },           \          { "TMS390Z50",          8, 0, 32, 8, 14,5,2, 14,5,2,  0,0,0 },  \
67          { "MB86904",            32, 14,5,2, 13,4,2,  0,0,0 },           \          { "MB86904",            8, 0, 32, 8, 14,5,2, 13,4,2,  0,0,0 },  \
68          { "MB86907",            32, 14,5,2, 14,5,2, 19,5,1 },           \          { "MB86907",            8, 0, 32, 8, 14,5,2, 14,5,2, 19,5,1 },  \
69          { "UltraSPARC",         64, 14,5,4, 14,5,4, 19,6,1 },           \          { "UltraSPARC",         9, 0, 64, 8, 14,5,4, 14,5,4, 19,6,1 },  \
70          { "UltraSPARC-IIi",     64, 15,5,2, 14,5,2, 21,6,1 },           \          { "UltraSPARC-IIi",     9, 0, 64, 8, 15,5,2, 14,5,2, 21,6,1 },  \
71          { "UltraSPARC-II",      64, 15,5,2, 14,5,2, 22,6,1 },           \          { "UltraSPARC-II",      9, 0, 64, 8, 15,5,2, 14,5,2, 22,6,1 },  \
72          { NULL,                 0,  0,0,0,  0,0,0,   0,0,0 }            \          { "T1",                 9, 1, 64, 8, 15,5,2, 14,5,2, 22,6,1 },  \
73            { NULL,                 0, 0,  0, 0,  0,0,0,  0,0,0,  0,0,0 }   \
74          }          }
75    
76    
# Line 83  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC Line 94  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC
94    
95    
96  #define N_SPARC_REG             32  #define N_SPARC_REG             32
97    #define N_SPARC_GLOBAL_REG      8
98    #define N_SPARC_INOUT_REG       8
99    #define N_SPARC_LOCAL_REG       8
100  #define SPARC_REG_NAMES {                               \  #define SPARC_REG_NAMES {                               \
101          "g0","g1","g2","g3","g4","g5","g6","g7",        \          "g0","g1","g2","g3","g4","g5","g6","g7",        \
102          "o0","o1","o2","o3","o4","o5","sp","o7",        \          "o0","o1","o2","o3","o4","o5","sp","o7",        \
# Line 128  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC Line 142  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC
142  #define SPARC_PREG_NAMES        {                                       \  #define SPARC_PREG_NAMES        {                                       \
143          "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",   \          "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",   \
144          "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",  \          "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",  \
145          "wstate", "reserved15", "reserved16", "reserved17", "reserved18", \          "wstate", "fq", "reserved16", "reserved17", "reserved18", \
146          "reserved19", "reserved20", "reserved21", "reserved22", \          "reserved19", "reserved20", "reserved21", "reserved22", \
147          "reserved23", "reserved24", "reserved25", "reserved26", \          "reserved23", "reserved24", "reserved25", "reserved26", \
148          "reserved27", "reserved28", "reserved29", "reserved30", \          "reserved27", "reserved28", "reserved29", "reserved30", \
149          "reserved31" }          "ver" }
150    
151  #define N_SPARC_BRANCH_TYPES    16  #define N_SPARC_BRANCH_TYPES    16
152  #define SPARC_BRANCH_NAMES {                                            \  #define SPARC_BRANCH_NAMES {                                            \
# Line 158  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC Line 172  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC
172    
173  #define N_LOADSTORE_TYPES       64  #define N_LOADSTORE_TYPES       64
174  #define SPARC_LOADSTORE_NAMES {                                         \  #define SPARC_LOADSTORE_NAMES {                                         \
175          "ld","ldub","lduh","ldd", "st","stb","sth","std",               \          "lduw","ldub","lduh","ldd", "st","stb","sth","std",             \
176          "[8]","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap",        \          "ldsw","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap",       \
177          "lda","lduba","lduha","ldda", "sta","stba","stha","stda",       \          "lda","lduba","lduha","ldda", "sta","stba","stha","stda",       \
178          "[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa",  \          "[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa",  \
179          "ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf",      \          "ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf",      \
# Line 168  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC Line 182  DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC
182          "[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" }          "[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" }
183    
184    
185  /*  Max number of Trap Levels and Windows:  */  /*  Max number of Trap Levels, Global Levels, and Register Windows:  */
186  #define MAXTL                   4  #define MAXTL                   6
187  #define MAXWIN                  32  #define MAXGL                   7
188    #define N_REG_WINDOWS           8
189    
190    
191  struct sparc_cpu {  struct sparc_cpu {
# Line 179  struct sparc_cpu { Line 194  struct sparc_cpu {
194          /*  Registers in the Current Window:  */          /*  Registers in the Current Window:  */
195          uint64_t        r[N_SPARC_REG];          uint64_t        r[N_SPARC_REG];
196    
197            uint64_t        r_inout[N_REG_WINDOWS][N_SPARC_INOUT_REG];
198            uint64_t        r_local[N_REG_WINDOWS][N_SPARC_LOCAL_REG];
199    
200            uint64_t        r_global[MAXGL+1][N_SPARC_GLOBAL_REG];
201    
202          uint64_t        scratch;          uint64_t        scratch;
203    
204          /*  Pre-SPARCv9 specific:  */          /*  Pre-SPARCv9 specific:  */
# Line 205  struct sparc_cpu { Line 225  struct sparc_cpu {
225          uint8_t         ccr;            /*  Condition Code Register  */          uint8_t         ccr;            /*  Condition Code Register  */
226          uint8_t         asi;            /*  Address Space Identifier  */          uint8_t         asi;            /*  Address Space Identifier  */
227          uint8_t         tl;             /*  Trap Level Register  */          uint8_t         tl;             /*  Trap Level Register  */
228            uint8_t         gl;             /*  Global Level Register  */
229          uint8_t         pil;            /*  Processor Interrupt Level Reg.  */          uint8_t         pil;            /*  Processor Interrupt Level Reg.  */
230    
231          uint64_t        tpc[MAXTL];     /*  Trap Program Counter  */          uint64_t        tpc[MAXTL];     /*  Trap Program Counter  */
# Line 214  struct sparc_cpu { Line 235  struct sparc_cpu {
235    
236          uint64_t        tba;            /*  Trap Base Address  */          uint64_t        tba;            /*  Trap Base Address  */
237    
238            uint64_t        hpstate;        /*  Hyper-Privileged State Register  */
239            uint64_t        htstate[MAXTL]; /*  Hyper-Privileged Trap State  */
240            uint64_t        hintp;          /*  Hyper-Privileged InterruptPending */
241            uint64_t        htba;           /*  Hyper-Privileged Trap Base Addr  */
242            uint64_t        hver;           /*  Hyper-Privileged Version Reg.  */
243    
244    
245          /*          /*
246           *  Instruction translation cache and Virtual->Physical->Host           *  Instruction translation cache and Virtual->Physical->Host
247           *  address translation:           *  address translation:
# Line 240  struct sparc_cpu { Line 268  struct sparc_cpu {
268  #define SPARC_PSTATE_AG         0x001   /*  Alternate Globals  */  #define SPARC_PSTATE_AG         0x001   /*  Alternate Globals  */
269    
270    
271    /*  Hyper-Privileged State Register (HPSTATE) bit definitions:  */
272    #define SPARC_HPSTATE_ID        0x800
273    #define SPARC_HPSTATE_IBE       0x400   /*  Instruction Break Enable  */
274    #define SPARC_HPSTATE_RED       0x020   /*  Reset/Error/Debug state  */
275    #define SPARC_HPSTATE_HPRIV     0x004   /*  Hyper-Privileged mode  */
276    #define SPARC_HPSTATE_TLZ       0x001   /*  Trap Level Zero trap enable  */
277    
278    
279  /*  Condition Code Register bit definitions:  */  /*  Condition Code Register bit definitions:  */
280  #define SPARC_CCR_XCC_MASK      0xf0  #define SPARC_CCR_XCC_MASK      0xf0
281  #define SPARC_CCR_XCC_SHIFT     4  #define SPARC_CCR_XCC_SHIFT     4
# Line 302  struct sparc_cpu { Line 338  struct sparc_cpu {
338    
339  /*  cpu_sparc.c:  */  /*  cpu_sparc.c:  */
340  int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);  int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
341    int sparc_run_instr(struct cpu *cpu);
342  void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
343          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
344  void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
345  void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
346    int sparc32_run_instr(struct cpu *cpu);
347  void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
348          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
349  void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
# Line 315  int sparc_memory_rw(struct cpu *cpu, str Line 353  int sparc_memory_rw(struct cpu *cpu, str
353          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
354  int sparc_cpu_family_init(struct cpu_family *);  int sparc_cpu_family_init(struct cpu_family *);
355    
356    /*  memory_sparc.c:  */
357    int sparc_translate_v2p(struct cpu *cpu, uint64_t vaddr,
358            uint64_t *return_addr, int flags);
359    
360    
361  #endif  /*  CPU_SPARC_H  */  #endif  /*  CPU_SPARC_H  */

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