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#define CPU_SPARC_H |
#define CPU_SPARC_H |
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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_sparc.h,v 1.38 2006/05/18 05:10:44 debug Exp $ |
* $Id: cpu_sparc.h,v 1.46 2007/03/16 18:49:06 debug Exp $ |
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*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
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/* SPARC CPU types: */ |
/* SPARC CPU types: */ |
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struct sparc_cpu_type_def { |
struct sparc_cpu_type_def { |
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char *name; |
char *name; |
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int bits; |
int v; /* v8, v9 etc */ |
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int h; /* hypervisor? sun4v = 1 */ |
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int bits; /* 32 or 64 */ |
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int nwindows; /* usually 8 or more */ |
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int icache_shift; |
int icache_shift; |
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int ilinesize; |
int ilinesize; |
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int iway; |
int iway; |
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int l2way; |
int l2way; |
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}; |
}; |
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/* NOTE/TODO: Maybe some of the types listed below as v8 are in |
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fact v7; I haven't had time to check. Also, the nwindows value is |
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just bogus. */ |
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/* See http://www.sparc.com/standards/v8v9-numbers.html for |
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implementation numbers! */ |
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/* Note/TODO: sun4v is listed as 10 */ |
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#define SPARC_CPU_TYPE_DEFS { \ |
#define SPARC_CPU_TYPE_DEFS { \ |
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{ "TMS390Z50", 32, 14,5,2, 14,5,2, 0,0,0 }, \ |
{ "TMS390Z50", 8, 0, 32, 8, 14,5,2, 14,5,2, 0,0,0 }, \ |
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{ "MB86904", 32, 14,5,2, 13,4,2, 0,0,0 }, \ |
{ "MB86904", 8, 0, 32, 8, 14,5,2, 13,4,2, 0,0,0 }, \ |
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{ "MB86907", 32, 14,5,2, 14,5,2, 19,5,1 }, \ |
{ "MB86907", 8, 0, 32, 8, 14,5,2, 14,5,2, 19,5,1 }, \ |
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{ "UltraSPARC", 64, 14,5,4, 14,5,4, 19,6,1 }, \ |
{ "UltraSPARC", 9, 0, 64, 8, 14,5,4, 14,5,4, 19,6,1 }, \ |
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{ "UltraSPARC-IIi", 64, 15,5,2, 14,5,2, 21,6,1 }, \ |
{ "UltraSPARC-IIi", 9, 0, 64, 8, 15,5,2, 14,5,2, 21,6,1 }, \ |
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{ "UltraSPARC-II", 64, 15,5,2, 14,5,2, 22,6,1 }, \ |
{ "UltraSPARC-II", 9, 0, 64, 8, 15,5,2, 14,5,2, 22,6,1 }, \ |
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{ NULL, 0, 0,0,0, 0,0,0, 0,0,0 } \ |
{ "T1", 9, 1, 64, 8, 15,5,2, 14,5,2, 22,6,1 }, \ |
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{ NULL, 0, 0, 0, 0, 0,0,0, 0,0,0, 0,0,0 } \ |
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} |
} |
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#define N_SPARC_REG 32 |
#define N_SPARC_REG 32 |
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#define N_SPARC_GLOBAL_REG 8 |
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#define N_SPARC_INOUT_REG 8 |
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#define N_SPARC_LOCAL_REG 8 |
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#define SPARC_REG_NAMES { \ |
#define SPARC_REG_NAMES { \ |
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"g0","g1","g2","g3","g4","g5","g6","g7", \ |
"g0","g1","g2","g3","g4","g5","g6","g7", \ |
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"o0","o1","o2","o3","o4","o5","sp","o7", \ |
"o0","o1","o2","o3","o4","o5","sp","o7", \ |
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#define SPARC_PREG_NAMES { \ |
#define SPARC_PREG_NAMES { \ |
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"tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", \ |
"tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", \ |
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"pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", \ |
"pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", \ |
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"wstate", "reserved15", "reserved16", "reserved17", "reserved18", \ |
"wstate", "fq", "reserved16", "reserved17", "reserved18", \ |
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"reserved19", "reserved20", "reserved21", "reserved22", \ |
"reserved19", "reserved20", "reserved21", "reserved22", \ |
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"reserved23", "reserved24", "reserved25", "reserved26", \ |
"reserved23", "reserved24", "reserved25", "reserved26", \ |
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"reserved27", "reserved28", "reserved29", "reserved30", \ |
"reserved27", "reserved28", "reserved29", "reserved30", \ |
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"reserved31" } |
"ver" } |
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#define N_SPARC_BRANCH_TYPES 16 |
#define N_SPARC_BRANCH_TYPES 16 |
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#define SPARC_BRANCH_NAMES { \ |
#define SPARC_BRANCH_NAMES { \ |
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#define N_LOADSTORE_TYPES 64 |
#define N_LOADSTORE_TYPES 64 |
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#define SPARC_LOADSTORE_NAMES { \ |
#define SPARC_LOADSTORE_NAMES { \ |
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"ld","ldub","lduh","ldd", "st","stb","sth","std", \ |
"lduw","ldub","lduh","ldd", "st","stb","sth","std", \ |
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"[8]","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap", \ |
"ldsw","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap", \ |
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"lda","lduba","lduha","ldda", "sta","stba","stha","stda", \ |
"lda","lduba","lduha","ldda", "sta","stba","stha","stda", \ |
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"[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa", \ |
"[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa", \ |
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"ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf", \ |
"ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf", \ |
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"[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" } |
"[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" } |
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/* Max number of Trap Levels and Windows: */ |
/* Max number of Trap Levels, Global Levels, and Register Windows: */ |
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#define MAXTL 4 |
#define MAXTL 6 |
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#define MAXWIN 32 |
#define MAXGL 7 |
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#define N_REG_WINDOWS 8 |
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struct sparc_cpu { |
struct sparc_cpu { |
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/* Registers in the Current Window: */ |
/* Registers in the Current Window: */ |
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uint64_t r[N_SPARC_REG]; |
uint64_t r[N_SPARC_REG]; |
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uint64_t r_inout[N_REG_WINDOWS][N_SPARC_INOUT_REG]; |
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uint64_t r_local[N_REG_WINDOWS][N_SPARC_LOCAL_REG]; |
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uint64_t r_global[MAXGL+1][N_SPARC_GLOBAL_REG]; |
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uint64_t scratch; |
uint64_t scratch; |
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/* Pre-SPARCv9 specific: */ |
/* Pre-SPARCv9 specific: */ |
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uint8_t ccr; /* Condition Code Register */ |
uint8_t ccr; /* Condition Code Register */ |
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uint8_t asi; /* Address Space Identifier */ |
uint8_t asi; /* Address Space Identifier */ |
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uint8_t tl; /* Trap Level Register */ |
uint8_t tl; /* Trap Level Register */ |
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uint8_t gl; /* Global Level Register */ |
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uint8_t pil; /* Processor Interrupt Level Reg. */ |
uint8_t pil; /* Processor Interrupt Level Reg. */ |
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uint64_t tpc[MAXTL]; /* Trap Program Counter */ |
uint64_t tpc[MAXTL]; /* Trap Program Counter */ |
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uint64_t tba; /* Trap Base Address */ |
uint64_t tba; /* Trap Base Address */ |
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uint64_t hpstate; /* Hyper-Privileged State Register */ |
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uint64_t htstate[MAXTL]; /* Hyper-Privileged Trap State */ |
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uint64_t hintp; /* Hyper-Privileged InterruptPending */ |
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uint64_t htba; /* Hyper-Privileged Trap Base Addr */ |
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uint64_t hver; /* Hyper-Privileged Version Reg. */ |
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/* |
/* |
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* Instruction translation cache and Virtual->Physical->Host |
* Instruction translation cache and Virtual->Physical->Host |
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* address translation: |
* address translation: |
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#define SPARC_PSTATE_AG 0x001 /* Alternate Globals */ |
#define SPARC_PSTATE_AG 0x001 /* Alternate Globals */ |
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/* Hyper-Privileged State Register (HPSTATE) bit definitions: */ |
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#define SPARC_HPSTATE_ID 0x800 |
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#define SPARC_HPSTATE_IBE 0x400 /* Instruction Break Enable */ |
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#define SPARC_HPSTATE_RED 0x020 /* Reset/Error/Debug state */ |
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#define SPARC_HPSTATE_HPRIV 0x004 /* Hyper-Privileged mode */ |
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#define SPARC_HPSTATE_TLZ 0x001 /* Trap Level Zero trap enable */ |
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/* Condition Code Register bit definitions: */ |
/* Condition Code Register bit definitions: */ |
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#define SPARC_CCR_XCC_MASK 0xf0 |
#define SPARC_CCR_XCC_MASK 0xf0 |
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#define SPARC_CCR_XCC_SHIFT 4 |
#define SPARC_CCR_XCC_SHIFT 4 |
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/* cpu_sparc.c: */ |
/* cpu_sparc.c: */ |
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int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
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int sparc_run_instr(struct cpu *cpu); |
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void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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int sparc32_run_instr(struct cpu *cpu); |
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void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int sparc_cpu_family_init(struct cpu_family *); |
int sparc_cpu_family_init(struct cpu_family *); |
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/* memory_sparc.c: */ |
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int sparc_translate_v2p(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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#endif /* CPU_SPARC_H */ |
#endif /* CPU_SPARC_H */ |