src/include/cpu_sparc.h

#ifndef CPU_SPARC_H
#define CPU_SPARC_H

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_sparc.h,v 1.15 2005/11/16 21:15:19 debug Exp $
 */

#include "misc.h"


struct cpu_family;


#define SPARC_N_IC_ARGS                 3
#define SPARC_INSTR_ALIGNMENT_SHIFT     2
#define SPARC_IC_ENTRIES_SHIFT          10
#define SPARC_IC_ENTRIES_PER_PAGE       (1 << SPARC_IC_ENTRIES_SHIFT)
#define SPARC_PC_TO_IC_ENTRY(a)         (((a)>>SPARC_INSTR_ALIGNMENT_SHIFT) \
                                        & (SPARC_IC_ENTRIES_PER_PAGE-1))
#define SPARC_ADDR_TO_PAGENR(a)         ((a) >> (SPARC_IC_ENTRIES_SHIFT \
                                        + SPARC_INSTR_ALIGNMENT_SHIFT))

struct sparc_instr_call {
        void    (*f)(struct cpu *, struct sparc_instr_call *);
        size_t  arg[SPARC_N_IC_ARGS];
};

/*  Translation cache struct for each physical page:  */
struct sparc_tc_physpage {
        struct sparc_instr_call ics[SPARC_IC_ENTRIES_PER_PAGE + 1];
        uint32_t        next_ofs;       /*  or 0 for end of chain  */
        int             flags;
        uint64_t        physaddr;
};

#define SPARC_N_VPH_ENTRIES             1048576

#define SPARC_MAX_VPH_TLB_ENTRIES               256
struct sparc_vpg_tlb_entry {
        uint8_t         valid;
        uint8_t         writeflag;
        unsigned char   *host_page;
        int64_t         timestamp;
        uint64_t        vaddr_page;
        uint64_t        paddr_page;
};

struct sparc_cpu {
        /*  TODO  */
        uint64_t        r_i[8];


        /*
         *  Instruction translation cache:
         */

        /*  cur_ic_page is a pointer to an array of SPARC_IC_ENTRIES_PER_PAGE
            instruction call entries. next_ic points to the next such
            call to be executed.  */
        struct sparc_tc_physpage        *cur_physpage;
        struct sparc_instr_call *cur_ic_page;
        struct sparc_instr_call *next_ic;

        void                    (*combination_check)(struct cpu *,
                                    struct sparc_instr_call *, int low_addr);

        /*
         *  Virtual -> physical -> host address translation:
         *
         *  host_load and host_store point to arrays of SPARC_N_VPH_ENTRIES
         *  pointers (to host pages); phys_addr points to an array of
         *  SPARC_N_VPH_ENTRIES uint32_t.
         */

        struct sparc_vpg_tlb_entry  vph_tlb_entry[SPARC_MAX_VPH_TLB_ENTRIES];
        unsigned char               *host_load[SPARC_N_VPH_ENTRIES]; 
        unsigned char               *host_store[SPARC_N_VPH_ENTRIES];
        uint32_t                    phys_addr[SPARC_N_VPH_ENTRIES]; 
        struct sparc_tc_physpage    *phys_page[SPARC_N_VPH_ENTRIES];

        uint32_t                    phystranslation[SPARC_N_VPH_ENTRIES/32];
        uint8_t                     vaddr_to_tlbindex[SPARC_N_VPH_ENTRIES];
};


/*  cpu_sparc.c:  */
void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int sparc_cpu_family_init(struct cpu_family *);


#endif  /*  CPU_SPARC_H  */
1	#ifndef CPU_SPARC_H
2	#define CPU_SPARC_H
3
4	/*
5	* Copyright (C) 2005 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu_sparc.h,v 1.15 2005/11/16 21:15:19 debug Exp $
32	*/
33
34	#include "misc.h"
35
36
37	struct cpu_family;
38
39
40	#define SPARC_N_IC_ARGS 3
41	#define SPARC_INSTR_ALIGNMENT_SHIFT 2
42	#define SPARC_IC_ENTRIES_SHIFT 10
43	#define SPARC_IC_ENTRIES_PER_PAGE (1 << SPARC_IC_ENTRIES_SHIFT)
44	#define SPARC_PC_TO_IC_ENTRY(a) (((a)>>SPARC_INSTR_ALIGNMENT_SHIFT) \
45	& (SPARC_IC_ENTRIES_PER_PAGE-1))
46	#define SPARC_ADDR_TO_PAGENR(a) ((a) >> (SPARC_IC_ENTRIES_SHIFT \
47	+ SPARC_INSTR_ALIGNMENT_SHIFT))
48
49	struct sparc_instr_call {
50	void (f)(struct cpu , struct sparc_instr_call *);
51	size_t arg[SPARC_N_IC_ARGS];
52	};
53
54	/* Translation cache struct for each physical page: */
55	struct sparc_tc_physpage {
56	struct sparc_instr_call ics[SPARC_IC_ENTRIES_PER_PAGE + 1];
57	uint32_t next_ofs; /* or 0 for end of chain */
58	int flags;
59	uint64_t physaddr;
60	};
61
62	#define SPARC_N_VPH_ENTRIES 1048576
63
64	#define SPARC_MAX_VPH_TLB_ENTRIES 256
65	struct sparc_vpg_tlb_entry {
66	uint8_t valid;
67	uint8_t writeflag;
68	unsigned char *host_page;
69	int64_t timestamp;
70	uint64_t vaddr_page;
71	uint64_t paddr_page;
72	};
73
74	struct sparc_cpu {
75	/* TODO */
76	uint64_t r_i[8];
77
78
79	/*
80	* Instruction translation cache:
81	*/
82
83	/* cur_ic_page is a pointer to an array of SPARC_IC_ENTRIES_PER_PAGE
84	instruction call entries. next_ic points to the next such
85	call to be executed. */
86	struct sparc_tc_physpage *cur_physpage;
87	struct sparc_instr_call *cur_ic_page;
88	struct sparc_instr_call *next_ic;
89
90	void (combination_check)(struct cpu ,
91	struct sparc_instr_call *, int low_addr);
92
93	/*
94	* Virtual -> physical -> host address translation:
95	*
96	* host_load and host_store point to arrays of SPARC_N_VPH_ENTRIES
97	* pointers (to host pages); phys_addr points to an array of
98	* SPARC_N_VPH_ENTRIES uint32_t.
99	*/
100
101	struct sparc_vpg_tlb_entry vph_tlb_entry[SPARC_MAX_VPH_TLB_ENTRIES];
102	unsigned char *host_load[SPARC_N_VPH_ENTRIES];
103	unsigned char *host_store[SPARC_N_VPH_ENTRIES];
104	uint32_t phys_addr[SPARC_N_VPH_ENTRIES];
105	struct sparc_tc_physpage *phys_page[SPARC_N_VPH_ENTRIES];
106
107	uint32_t phystranslation[SPARC_N_VPH_ENTRIES/32];
108	uint8_t vaddr_to_tlbindex[SPARC_N_VPH_ENTRIES];
109	};
110
111
112	/* cpu_sparc.c: */
113	void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
114	unsigned char *host_page, int writeflag, uint64_t paddr_page);
115	void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
116	void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
117	int sparc_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
118	unsigned char *data, size_t len, int writeflag, int cache_flags);
119	int sparc_cpu_family_init(struct cpu_family *);
120
121
122	#endif /* CPU_SPARC_H */