--- trunk/src/include/cpu_sparc.h	2007/10/08 16:21:26	35
+++ trunk/src/include/cpu_sparc.h	2007/10/08 16:21:34	36
@@ -28,7 +28,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_sparc.h,v 1.43 2006/12/30 13:31:00 debug Exp $
+ *  $Id: cpu_sparc.h,v 1.46 2007/03/16 18:49:06 debug Exp $
  */
 
 #include "misc.h"
@@ -41,6 +41,7 @@
 struct sparc_cpu_type_def { 
 	char		*name;
 	int		v;			/*  v8, v9 etc  */
+	int		h;			/*  hypervisor? sun4v = 1  */
 	int		bits;			/*  32 or 64  */
 	int		nwindows;		/*  usually 8 or more  */
 	int		icache_shift;
@@ -59,15 +60,17 @@
     just bogus.  */
 /*  See http://www.sparc.com/standards/v8v9-numbers.html for
     implementation numbers!  */
+/*  Note/TODO: sun4v is listed as 10  */
 
 #define SPARC_CPU_TYPE_DEFS	{					\
-	{ "TMS390Z50",		8, 32, 8, 14,5,2, 14,5,2,  0,0,0 },	\
-	{ "MB86904",		8, 32, 8, 14,5,2, 13,4,2,  0,0,0 },	\
-	{ "MB86907",		8, 32, 8, 14,5,2, 14,5,2, 19,5,1 },	\
-	{ "UltraSPARC",		9, 64, 8, 14,5,4, 14,5,4, 19,6,1 },	\
-	{ "UltraSPARC-IIi",	9, 64, 8, 15,5,2, 14,5,2, 21,6,1 },	\
-	{ "UltraSPARC-II",	9, 64, 8, 15,5,2, 14,5,2, 22,6,1 },	\
-	{ NULL,			0,  0, 0,  0,0,0,  0,0,0,  0,0,0 }	\
+	{ "TMS390Z50",		8, 0, 32, 8, 14,5,2, 14,5,2,  0,0,0 },	\
+	{ "MB86904",		8, 0, 32, 8, 14,5,2, 13,4,2,  0,0,0 },	\
+	{ "MB86907",		8, 0, 32, 8, 14,5,2, 14,5,2, 19,5,1 },	\
+	{ "UltraSPARC",		9, 0, 64, 8, 14,5,4, 14,5,4, 19,6,1 },	\
+	{ "UltraSPARC-IIi",	9, 0, 64, 8, 15,5,2, 14,5,2, 21,6,1 },	\
+	{ "UltraSPARC-II",	9, 0, 64, 8, 15,5,2, 14,5,2, 22,6,1 },	\
+	{ "T1",			9, 1, 64, 8, 15,5,2, 14,5,2, 22,6,1 },	\
+	{ NULL,			0, 0,  0, 0,  0,0,0,  0,0,0,  0,0,0 }	\
 	}
 
 
@@ -91,6 +94,7 @@
 
 
 #define	N_SPARC_REG		32
+#define	N_SPARC_GLOBAL_REG	8
 #define	N_SPARC_INOUT_REG	8
 #define	N_SPARC_LOCAL_REG	8
 #define	SPARC_REG_NAMES	{				\
@@ -178,9 +182,10 @@
 	"[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" }
 
 
-/*  Max number of Trap Levels and Windows:  */
-#define	MAXTL			4
-#define	MAXWIN			32
+/*  Max number of Trap Levels, Global Levels, and Register Windows:  */
+#define	MAXTL			6
+#define	MAXGL			7
+#define	N_REG_WINDOWS		8
 
 
 struct sparc_cpu {
@@ -189,8 +194,10 @@
 	/*  Registers in the Current Window:  */
 	uint64_t	r[N_SPARC_REG];
 
-	uint64_t	r_inout[MAXWIN][N_SPARC_INOUT_REG];
-	uint64_t	r_local[MAXWIN][N_SPARC_LOCAL_REG];
+	uint64_t	r_inout[N_REG_WINDOWS][N_SPARC_INOUT_REG];
+	uint64_t	r_local[N_REG_WINDOWS][N_SPARC_LOCAL_REG];
+
+	uint64_t	r_global[MAXGL+1][N_SPARC_GLOBAL_REG];
 
 	uint64_t	scratch;
 
@@ -218,6 +225,7 @@
 	uint8_t		ccr;		/*  Condition Code Register  */
 	uint8_t		asi;		/*  Address Space Identifier  */
 	uint8_t		tl;		/*  Trap Level Register  */
+	uint8_t		gl;		/*  Global Level Register  */
 	uint8_t		pil;		/*  Processor Interrupt Level Reg.  */
 
 	uint64_t	tpc[MAXTL];	/*  Trap Program Counter  */
@@ -227,6 +235,13 @@
 
 	uint64_t	tba;		/*  Trap Base Address  */
 
+	uint64_t	hpstate;	/*  Hyper-Privileged State Register  */
+	uint64_t	htstate[MAXTL];	/*  Hyper-Privileged Trap State  */
+	uint64_t	hintp;		/*  Hyper-Privileged InterruptPending */
+	uint64_t	htba;		/*  Hyper-Privileged Trap Base Addr  */
+	uint64_t	hver;		/*  Hyper-Privileged Version Reg.  */
+
+
 	/*
 	 *  Instruction translation cache and Virtual->Physical->Host
 	 *  address translation:
@@ -253,6 +268,14 @@
 #define	SPARC_PSTATE_AG		0x001	/*  Alternate Globals  */
 
 
+/*  Hyper-Privileged State Register (HPSTATE) bit definitions:  */
+#define	SPARC_HPSTATE_ID	0x800
+#define	SPARC_HPSTATE_IBE	0x400	/*  Instruction Break Enable  */
+#define	SPARC_HPSTATE_RED	0x020	/*  Reset/Error/Debug state  */
+#define	SPARC_HPSTATE_HPRIV	0x004	/*  Hyper-Privileged mode  */
+#define	SPARC_HPSTATE_TLZ	0x001	/*  Trap Level Zero trap enable  */
+
+
 /*  Condition Code Register bit definitions:  */
 #define	SPARC_CCR_XCC_MASK	0xf0
 #define	SPARC_CCR_XCC_SHIFT	4