/[gxemul]/trunk/src/include/cpu_sparc.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 21 by dpavlin, Mon Oct 8 16:19:23 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 2  Line 2 
2  #define CPU_SPARC_H  #define CPU_SPARC_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_sparc.h,v 1.15 2005/11/16 21:15:19 debug Exp $   *  $Id: cpu_sparc.h,v 1.23 2006/02/13 04:23:25 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 37  Line 37 
37  struct cpu_family;  struct cpu_family;
38    
39    
40    /*  SPARC CPU types:  */
41    struct sparc_cpu_type_def {
42            char            *name;
43            int             bits;
44            int             icache_shift;
45            int             ilinesize;
46            int             iway;
47            int             dcache_shift;
48            int             dlinesize;
49            int             dway;
50            int             l2cache_shift;
51            int             l2linesize;
52            int             l2way;
53    };
54    
55    #define SPARC_CPU_TYPE_DEFS     {                                       \
56            { "SPARCv7",    32, 14,5,4, 14,5,4, 0,0,0 },                    \
57            { "SPARCv9",    64, 14,5,4, 14,5,4, 0,0,0 },                    \
58            { NULL,         0,  0,0,0,  0,0,0,  0,0,0 }                     \
59            }
60    
61    
62  #define SPARC_N_IC_ARGS                 3  #define SPARC_N_IC_ARGS                 3
63  #define SPARC_INSTR_ALIGNMENT_SHIFT     2  #define SPARC_INSTR_ALIGNMENT_SHIFT     2
64  #define SPARC_IC_ENTRIES_SHIFT          10  #define SPARC_IC_ENTRIES_SHIFT          10
# Line 46  struct cpu_family; Line 68  struct cpu_family;
68  #define SPARC_ADDR_TO_PAGENR(a)         ((a) >> (SPARC_IC_ENTRIES_SHIFT \  #define SPARC_ADDR_TO_PAGENR(a)         ((a) >> (SPARC_IC_ENTRIES_SHIFT \
69                                          + SPARC_INSTR_ALIGNMENT_SHIFT))                                          + SPARC_INSTR_ALIGNMENT_SHIFT))
70    
71  struct sparc_instr_call {  DYNTRANS_MISC_DECLARATIONS(sparc,SPARC,uint64_t)
         void    (*f)(struct cpu *, struct sparc_instr_call *);  
         size_t  arg[SPARC_N_IC_ARGS];  
 };  
72    
73  /*  Translation cache struct for each physical page:  */  #define SPARC_MAX_VPH_TLB_ENTRIES               128
 struct sparc_tc_physpage {  
         struct sparc_instr_call ics[SPARC_IC_ENTRIES_PER_PAGE + 1];  
         uint32_t        next_ofs;       /*  or 0 for end of chain  */  
         int             flags;  
         uint64_t        physaddr;  
 };  
74    
 #define SPARC_N_VPH_ENTRIES             1048576  
75    
76  #define SPARC_MAX_VPH_TLB_ENTRIES               256  #define N_SPARC_REG             32
77  struct sparc_vpg_tlb_entry {  #define SPARC_REG_NAMES {                               \
78          uint8_t         valid;          "g0","g1","g2","g3","g4","g5","g6","g7",        \
79          uint8_t         writeflag;          "o0","o1","o2","o3","o4","o5","sp","o7",        \
80          unsigned char   *host_page;          "l0","l1","l2","l3","l4","l5","l6","l7",        \
81          int64_t         timestamp;          "i0","i1","i2","i3","i4","i5","fp","i7" }
82          uint64_t        vaddr_page;  
83          uint64_t        paddr_page;  #define N_SPARC_BRANCH_TYPES    16
84  };  #define SPARC_BRANCH_NAMES {                                            \
85            "bn", "be",  "ble", "bl",  "bleu", "bcs", "bneg", "bvs",        \
86            "b",  "bne", "bg",  "bge", "bgu",  "bcc", "bpos", "bvc"  }
87    
88    #define N_SPARC_REGBRANCH_TYPES 8
89    #define SPARC_REGBRANCH_NAMES {                                         \
90            "br?","brz","brlez","brlz","br??","brnz", "brgz", "brgez"  }
91    
92    #define N_ALU_INSTR_TYPES       64
93    #define SPARC_ALU_NAMES {                                               \
94            "add", "and", "or", "xor", "sub", "andn", "orn", "xnor",        \
95            "addx", "[9]", "umul", "smul", "subx", "[13]", "udiv", "sdiv",  \
96            "addcc","andcc","orcc","xorcc","subcc","andncc","orncc","xnorcc",\
97            "addxcc","[25]","umulcc","smulcc","subxcc","[29]","udivcc","sdivcc",\
98            "taddcc","tsubcc","taddcctv","tsubcctv","mulscc","sll","srl","sra",\
99            "[40]","[41]","[42]","[43]", "[44]","[45]","[46]","movre",      \
100            "[48]","[49]","[50]","[51]", "[52]","[53]","[54]","[55]",       \
101            "jmpl", "rett", "trap", "flush", "save", "restore", "[62]","[63]" }
102    
103    #define N_LOADSTORE_TYPES       64
104    #define SPARC_LOADSTORE_NAMES {                                         \
105            "ld","ldub","lduh","ldd", "st","stb","sth","std",               \
106            "[8]","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap",        \
107            "lda","lduba","lduha","ldda", "sta","stba","stha","stda",       \
108            "[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa",  \
109            "ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf",      \
110            "[40]","[41]","[42]","[43]", "[44]","[45]","[46]","[47]",       \
111            "ldc","ldcsr","[50]","lddc", "stc","stcsr","scdfq","scdf",      \
112            "[56]","[57]","[58]","[59]", "[60]","[61]","casxa","[63]" }
113    
114  struct sparc_cpu {  struct sparc_cpu {
115          /*  TODO  */          struct sparc_cpu_type_def cpu_type;
         uint64_t        r_i[8];  
116    
117            uint64_t        r[N_SPARC_REG];
118            uint64_t        zero;                   /*  for dyntrans; ALWAYS zero */
119    
         /*  
          *  Instruction translation cache:  
          */  
   
         /*  cur_ic_page is a pointer to an array of SPARC_IC_ENTRIES_PER_PAGE  
             instruction call entries. next_ic points to the next such  
             call to be executed.  */  
         struct sparc_tc_physpage        *cur_physpage;  
         struct sparc_instr_call *cur_ic_page;  
         struct sparc_instr_call *next_ic;  
   
         void                    (*combination_check)(struct cpu *,  
                                     struct sparc_instr_call *, int low_addr);  
120    
121          /*          /*
122           *  Virtual -> physical -> host address translation:           *  Instruction translation cache and Virtual->Physical->Host
123           *           *  address translation:
          *  host_load and host_store point to arrays of SPARC_N_VPH_ENTRIES  
          *  pointers (to host pages); phys_addr points to an array of  
          *  SPARC_N_VPH_ENTRIES uint32_t.  
124           */           */
125            DYNTRANS_ITC(sparc)
126          struct sparc_vpg_tlb_entry  vph_tlb_entry[SPARC_MAX_VPH_TLB_ENTRIES];          VPH_TLBS(sparc,SPARC)
127          unsigned char               *host_load[SPARC_N_VPH_ENTRIES];          VPH32(sparc,SPARC,uint64_t,uint8_t)
128          unsigned char               *host_store[SPARC_N_VPH_ENTRIES];          VPH64(sparc,SPARC,uint8_t)
         uint32_t                    phys_addr[SPARC_N_VPH_ENTRIES];  
         struct sparc_tc_physpage    *phys_page[SPARC_N_VPH_ENTRIES];  
   
         uint32_t                    phystranslation[SPARC_N_VPH_ENTRIES/32];  
         uint8_t                     vaddr_to_tlbindex[SPARC_N_VPH_ENTRIES];  
129  };  };
130    
131    
# Line 114  void sparc_update_translation_table(stru Line 134  void sparc_update_translation_table(stru
134          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
135  void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
136  void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
137    void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
138            unsigned char *host_page, int writeflag, uint64_t paddr_page);
139    void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
140    void sparc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
141  int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
142          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
143  int sparc_cpu_family_init(struct cpu_family *);  int sparc_cpu_family_init(struct cpu_family *);

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