28 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
29 |
* |
* |
30 |
* |
* |
31 |
* $Id: cpu_sparc.h,v 1.23 2006/02/13 04:23:25 debug Exp $ |
* $Id: cpu_sparc.h,v 1.38 2006/05/18 05:10:44 debug Exp $ |
32 |
*/ |
*/ |
33 |
|
|
34 |
#include "misc.h" |
#include "misc.h" |
53 |
}; |
}; |
54 |
|
|
55 |
#define SPARC_CPU_TYPE_DEFS { \ |
#define SPARC_CPU_TYPE_DEFS { \ |
56 |
{ "SPARCv7", 32, 14,5,4, 14,5,4, 0,0,0 }, \ |
{ "TMS390Z50", 32, 14,5,2, 14,5,2, 0,0,0 }, \ |
57 |
{ "SPARCv9", 64, 14,5,4, 14,5,4, 0,0,0 }, \ |
{ "MB86904", 32, 14,5,2, 13,4,2, 0,0,0 }, \ |
58 |
{ NULL, 0, 0,0,0, 0,0,0, 0,0,0 } \ |
{ "MB86907", 32, 14,5,2, 14,5,2, 19,5,1 }, \ |
59 |
|
{ "UltraSPARC", 64, 14,5,4, 14,5,4, 19,6,1 }, \ |
60 |
|
{ "UltraSPARC-IIi", 64, 15,5,2, 14,5,2, 21,6,1 }, \ |
61 |
|
{ "UltraSPARC-II", 64, 15,5,2, 14,5,2, 22,6,1 }, \ |
62 |
|
{ NULL, 0, 0,0,0, 0,0,0, 0,0,0 } \ |
63 |
} |
} |
64 |
|
|
65 |
|
|
72 |
#define SPARC_ADDR_TO_PAGENR(a) ((a) >> (SPARC_IC_ENTRIES_SHIFT \ |
#define SPARC_ADDR_TO_PAGENR(a) ((a) >> (SPARC_IC_ENTRIES_SHIFT \ |
73 |
+ SPARC_INSTR_ALIGNMENT_SHIFT)) |
+ SPARC_INSTR_ALIGNMENT_SHIFT)) |
74 |
|
|
75 |
|
#define SPARC_L2N 17 |
76 |
|
#define SPARC_L3N 18 /* 4KB pages on 32-bit sparc, */ |
77 |
|
/* 8KB pages on 64-bit? TODO */ |
78 |
|
|
79 |
DYNTRANS_MISC_DECLARATIONS(sparc,SPARC,uint64_t) |
DYNTRANS_MISC_DECLARATIONS(sparc,SPARC,uint64_t) |
80 |
|
DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC,uint8_t) |
81 |
|
|
82 |
#define SPARC_MAX_VPH_TLB_ENTRIES 128 |
#define SPARC_MAX_VPH_TLB_ENTRIES 128 |
83 |
|
|
89 |
"l0","l1","l2","l3","l4","l5","l6","l7", \ |
"l0","l1","l2","l3","l4","l5","l6","l7", \ |
90 |
"i0","i1","i2","i3","i4","i5","fp","i7" } |
"i0","i1","i2","i3","i4","i5","fp","i7" } |
91 |
|
|
92 |
|
#define SPARC_ZEROREG 0 /* g0 */ |
93 |
|
#define SPARC_REG_G0 0 |
94 |
|
#define SPARC_REG_G1 1 |
95 |
|
#define SPARC_REG_G2 2 |
96 |
|
#define SPARC_REG_G3 3 |
97 |
|
#define SPARC_REG_G4 4 |
98 |
|
#define SPARC_REG_G5 5 |
99 |
|
#define SPARC_REG_G6 6 |
100 |
|
#define SPARC_REG_G7 7 |
101 |
|
#define SPARC_REG_O0 8 |
102 |
|
#define SPARC_REG_O1 9 |
103 |
|
#define SPARC_REG_O2 10 |
104 |
|
#define SPARC_REG_O3 11 |
105 |
|
#define SPARC_REG_O4 12 |
106 |
|
#define SPARC_REG_O5 13 |
107 |
|
#define SPARC_REG_O6 14 |
108 |
|
#define SPARC_REG_O7 15 |
109 |
|
#define SPARC_REG_L0 16 |
110 |
|
#define SPARC_REG_L1 17 |
111 |
|
#define SPARC_REG_L2 18 |
112 |
|
#define SPARC_REG_L3 19 |
113 |
|
#define SPARC_REG_L4 20 |
114 |
|
#define SPARC_REG_L5 21 |
115 |
|
#define SPARC_REG_L6 22 |
116 |
|
#define SPARC_REG_L7 23 |
117 |
|
#define SPARC_REG_I0 24 |
118 |
|
#define SPARC_REG_I1 25 |
119 |
|
#define SPARC_REG_I2 26 |
120 |
|
#define SPARC_REG_I3 27 |
121 |
|
#define SPARC_REG_I4 28 |
122 |
|
#define SPARC_REG_I5 29 |
123 |
|
#define SPARC_REG_I6 30 |
124 |
|
#define SPARC_REG_I7 31 |
125 |
|
|
126 |
|
/* Privileged registers: */ |
127 |
|
#define N_SPARC_PREG 32 |
128 |
|
#define SPARC_PREG_NAMES { \ |
129 |
|
"tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", \ |
130 |
|
"pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", \ |
131 |
|
"wstate", "reserved15", "reserved16", "reserved17", "reserved18", \ |
132 |
|
"reserved19", "reserved20", "reserved21", "reserved22", \ |
133 |
|
"reserved23", "reserved24", "reserved25", "reserved26", \ |
134 |
|
"reserved27", "reserved28", "reserved29", "reserved30", \ |
135 |
|
"reserved31" } |
136 |
|
|
137 |
#define N_SPARC_BRANCH_TYPES 16 |
#define N_SPARC_BRANCH_TYPES 16 |
138 |
#define SPARC_BRANCH_NAMES { \ |
#define SPARC_BRANCH_NAMES { \ |
139 |
"bn", "be", "ble", "bl", "bleu", "bcs", "bneg", "bvs", \ |
"bn", "be", "ble", "bl", "bleu", "bcs", "bneg", "bvs", \ |
140 |
"b", "bne", "bg", "bge", "bgu", "bcc", "bpos", "bvc" } |
"ba", "bne", "bg", "bge", "bgu", "bcc", "bpos", "bvc" } |
141 |
|
|
142 |
#define N_SPARC_REGBRANCH_TYPES 8 |
#define N_SPARC_REGBRANCH_TYPES 8 |
143 |
#define SPARC_REGBRANCH_NAMES { \ |
#define SPARC_REGBRANCH_NAMES { \ |
150 |
"addcc","andcc","orcc","xorcc","subcc","andncc","orncc","xnorcc",\ |
"addcc","andcc","orcc","xorcc","subcc","andncc","orncc","xnorcc",\ |
151 |
"addxcc","[25]","umulcc","smulcc","subxcc","[29]","udivcc","sdivcc",\ |
"addxcc","[25]","umulcc","smulcc","subxcc","[29]","udivcc","sdivcc",\ |
152 |
"taddcc","tsubcc","taddcctv","tsubcctv","mulscc","sll","srl","sra",\ |
"taddcc","tsubcc","taddcctv","tsubcctv","mulscc","sll","srl","sra",\ |
153 |
"[40]","[41]","[42]","[43]", "[44]","[45]","[46]","movre", \ |
"rd" /* membar/stbar on sparcv9 */, \ |
154 |
"[48]","[49]","[50]","[51]", "[52]","[53]","[54]","[55]", \ |
"rd" /* rd psr on pre-sparcv9 */, "rdpr","rd", \ |
155 |
|
"[44]","[45]","popc","movre", \ |
156 |
|
"wr*","saved/restored","wrpr","[51]", "[52]","[53]","[54]","[55]",\ |
157 |
"jmpl", "rett", "trap", "flush", "save", "restore", "[62]","[63]" } |
"jmpl", "rett", "trap", "flush", "save", "restore", "[62]","[63]" } |
158 |
|
|
159 |
#define N_LOADSTORE_TYPES 64 |
#define N_LOADSTORE_TYPES 64 |
163 |
"lda","lduba","lduha","ldda", "sta","stba","stha","stda", \ |
"lda","lduba","lduha","ldda", "sta","stba","stha","stda", \ |
164 |
"[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa", \ |
"[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa", \ |
165 |
"ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf", \ |
"ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf", \ |
166 |
"[40]","[41]","[42]","[43]", "[44]","[45]","[46]","[47]", \ |
"[40]","[41]","[42]","[43]", "[44]","prefetch","[46]","[47]", \ |
167 |
"ldc","ldcsr","[50]","lddc", "stc","stcsr","scdfq","scdf", \ |
"ldc","ldcsr","[50]","lddc", "stc","stcsr","scdfq","scdf", \ |
168 |
"[56]","[57]","[58]","[59]", "[60]","[61]","casxa","[63]" } |
"[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" } |
169 |
|
|
170 |
|
|
171 |
|
/* Max number of Trap Levels and Windows: */ |
172 |
|
#define MAXTL 4 |
173 |
|
#define MAXWIN 32 |
174 |
|
|
175 |
|
|
176 |
struct sparc_cpu { |
struct sparc_cpu { |
177 |
struct sparc_cpu_type_def cpu_type; |
struct sparc_cpu_type_def cpu_type; |
178 |
|
|
179 |
|
/* Registers in the Current Window: */ |
180 |
uint64_t r[N_SPARC_REG]; |
uint64_t r[N_SPARC_REG]; |
|
uint64_t zero; /* for dyntrans; ALWAYS zero */ |
|
181 |
|
|
182 |
|
uint64_t scratch; |
183 |
|
|
184 |
|
/* Pre-SPARCv9 specific: */ |
185 |
|
uint32_t psr; /* Processor State Register */ |
186 |
|
uint32_t tbr; /* Trap base register */ |
187 |
|
uint32_t wim; /* Window invalid mask */ |
188 |
|
|
189 |
|
/* SPARCv9 etc.: */ |
190 |
|
uint64_t pstate; /* Processor State Register */ |
191 |
|
uint64_t y; /* Y-reg (only low 32-bits used) */ |
192 |
|
uint64_t fprs; /* Floating Point Register Status */ |
193 |
|
uint64_t tick; /* Tick Register */ |
194 |
|
uint64_t tick_cmpr; /* Tick Compare Register (?) */ |
195 |
|
uint64_t ver; /* Version register */ |
196 |
|
|
197 |
|
uint8_t cwp; /* Current Window Pointer */ |
198 |
|
uint8_t cansave; /* CANSAVE register */ |
199 |
|
uint8_t canrestore; /* CANRESTORE register */ |
200 |
|
uint8_t otherwin; /* OTHERWIN register */ |
201 |
|
uint8_t cleanwin; /* CLEANWIN register */ |
202 |
|
|
203 |
|
uint8_t wstate; /* Window state */ |
204 |
|
|
205 |
|
uint8_t ccr; /* Condition Code Register */ |
206 |
|
uint8_t asi; /* Address Space Identifier */ |
207 |
|
uint8_t tl; /* Trap Level Register */ |
208 |
|
uint8_t pil; /* Processor Interrupt Level Reg. */ |
209 |
|
|
210 |
|
uint64_t tpc[MAXTL]; /* Trap Program Counter */ |
211 |
|
uint64_t tnpc[MAXTL]; /* Trap Next Program Counter */ |
212 |
|
uint64_t tstate[MAXTL]; /* Trap State */ |
213 |
|
uint32_t ttype[MAXTL]; /* Trap Type */ |
214 |
|
|
215 |
|
uint64_t tba; /* Trap Base Address */ |
216 |
|
|
217 |
/* |
/* |
218 |
* Instruction translation cache and Virtual->Physical->Host |
* Instruction translation cache and Virtual->Physical->Host |
225 |
}; |
}; |
226 |
|
|
227 |
|
|
228 |
|
/* Processor State Register (PSTATE) bit definitions: */ |
229 |
|
#define SPARC_PSTATE_PID1 0x800 |
230 |
|
#define SPARC_PSTATE_PID0 0x400 |
231 |
|
#define SPARC_PSTATE_CLE 0x200 /* Current Little Endian */ |
232 |
|
#define SPARC_PSTATE_TLE 0x100 /* Trap Little Endian */ |
233 |
|
#define SPARC_PSTATE_MM_MASK 0x0c0 /* Memory Model (TODO) */ |
234 |
|
#define SPARC_PSTATE_MM_SHIFT 6 |
235 |
|
#define SPARC_PSTATE_RED 0x020 /* Reset/Error/Debug state */ |
236 |
|
#define SPARC_PSTATE_PEF 0x010 /* Enable Floating-point */ |
237 |
|
#define SPARC_PSTATE_AM 0x008 /* Address Mask */ |
238 |
|
#define SPARC_PSTATE_PRIV 0x004 /* Privileged Mode */ |
239 |
|
#define SPARC_PSTATE_IE 0x002 /* Interrupt Enable */ |
240 |
|
#define SPARC_PSTATE_AG 0x001 /* Alternate Globals */ |
241 |
|
|
242 |
|
|
243 |
|
/* Condition Code Register bit definitions: */ |
244 |
|
#define SPARC_CCR_XCC_MASK 0xf0 |
245 |
|
#define SPARC_CCR_XCC_SHIFT 4 |
246 |
|
#define SPARC_CCR_ICC_MASK 0x0f |
247 |
|
#define SPARC_CCR_N 8 |
248 |
|
#define SPARC_CCR_Z 4 |
249 |
|
#define SPARC_CCR_V 2 |
250 |
|
#define SPARC_CCR_C 1 |
251 |
|
|
252 |
|
|
253 |
|
/* CWP, CANSAVE, CANRESTORE, OTHERWIN, CLEANWIN bitmask: */ |
254 |
|
#define SPARC_CWP_MASK 0x1f |
255 |
|
|
256 |
|
|
257 |
|
/* Window State bit definitions: */ |
258 |
|
#define SPARC_WSTATE_OTHER_MASK 0x38 |
259 |
|
#define SPARC_WSTATE_OTHER_SHIFT 3 |
260 |
|
#define SPARC_WSTATE_NORMAL_MASK 0x07 |
261 |
|
|
262 |
|
|
263 |
|
/* Tick Register bit definitions: */ |
264 |
|
#define SPARC_TICK_NPT (1ULL << 63) /* Non-privileged trap */ |
265 |
|
|
266 |
|
|
267 |
|
/* Addess Space Identifier bit definitions: */ |
268 |
|
#define SPARC_ASI_RESTRICTED 0x80 |
269 |
|
|
270 |
|
|
271 |
|
/* Trap Level Register bit definitions: */ |
272 |
|
#define SPARC_TL_MASK 0x07 |
273 |
|
|
274 |
|
|
275 |
|
/* Processor Interrupt Level Register bit definitions: */ |
276 |
|
#define SPARC_PIL_MASK 0x0f |
277 |
|
|
278 |
|
|
279 |
|
/* Trap Type Register bit definitions: */ |
280 |
|
#define SPARC_TTYPE_MASK 0x1ff |
281 |
|
|
282 |
|
|
283 |
|
/* Trap Base Address bit definitions: */ |
284 |
|
#define SPARC_TBA_MASK 0xffffffffffff8000ULL |
285 |
|
|
286 |
|
|
287 |
|
/* |
288 |
|
* Full address for a trap is: |
289 |
|
* TBA<bits 63..15> || X || TTYPE[TL] || 00000 |
290 |
|
* |
291 |
|
* where X is a bit which is true if TL>0 when the trap was taken. |
292 |
|
*/ |
293 |
|
|
294 |
|
|
295 |
|
/* Version Register bit definitions: */ |
296 |
|
#define SPARC_VER_MANUF_SHIFT 48 |
297 |
|
#define SPARC_VER_IMPL_SHIFT 32 |
298 |
|
#define SPARC_VER_MASK_SHIFT 24 |
299 |
|
#define SPARC_VER_MAXTL_SHIFT 8 |
300 |
|
#define SPARC_VER_MAXWIN_SHIFT 0 |
301 |
|
|
302 |
|
|
303 |
/* cpu_sparc.c: */ |
/* cpu_sparc.c: */ |
304 |
|
int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
305 |
void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
306 |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
307 |
void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
310 |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
311 |
void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
312 |
void sparc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
void sparc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
313 |
|
void sparc_init_64bit_dummy_tables(struct cpu *cpu); |
314 |
int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
315 |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
316 |
int sparc_cpu_family_init(struct cpu_family *); |
int sparc_cpu_family_init(struct cpu_family *); |