Parent Directory | Revision Log
++ trunk/HISTORY (local) $Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $ 20060816 Adding a framework for emulated/virtual timers (src/timer.c), using only setitimer(). Rewriting the mc146818 to use the new timer framework. 20060817 Adding a call to gettimeofday() every now and then (once every second, at the moment) to resynch the timer if it drifts. Beginning to convert the ISA timer interrupt mechanism (8253 and 8259) to use the new timer framework. Removing the -I command line option. 20060819 Adding the -I command line option again, with new semantics. Working on Footbridge timer interrupts; NetBSD/NetWinder and NetBSD/CATS now run at correct speed, but unfortunately with HUGE delays during bootup. 20060821 Some minor m68k updates. Adding the first instruction: nop. :) Minor Alpha emulation updates. 20060822 Adding a FreeBSD development specific YAMON environment variable ("khz") (as suggested by Bruce M. Simpson). Moving YAMON environment variable initialization from machine_evbmips.c into promemul/yamon.c, and adding some more variables. Continuing on the LCA PCI bus controller (for Alpha machines). 20060823 Continuing on the timer stuff: experimenting with MIPS count/ compare interrupts connected to the timer framework. 20060825 Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and 0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer, to allow NetBSD/pmax 4.0_BETA to be installed from CDROM. Minor updates to the LCA PCI controller. 20060827 Implementing a CHIP8 cpu mode, and a corresponding CHIP8 machine, for fun. Disassembly support for all instructions, and most of the common instructions have been implemented: mvi, mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr, skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub, font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne. 20060828 Beginning to convert the CHIP8 cpu in the CHIP8 machine to a (more correct) RCA 180x cpu. (Disassembly for all 1802 instructions has been implemented, but no execution yet, and no 1805 extended instructions.) 20060829 Minor Alpha emulation updates. 20060830 Beginning to experiment a little with PCI IDE for SGI O2. Fixing the cursor key mappings for MobilePro 770 emulation. Fixing the LK201 warning caused by recent NetBSD/pmax. The MIPS R41xx standby, suspend, and hibernate instructions now behave like the RM52xx/MIPS32/MIPS64 wait instruction. Fixing dev_wdc so it calculates correct (64-bit) offsets before giving them to diskimage_access(). 20060831 Continuing on Alpha emulation (OSF1 PALcode). 20060901 Minor Alpha updates; beginning on virtual memory pagetables. Removed the limit for max nr of devices (in preparation for allowing devices' base addresses to be changed during runtime). Adding a hack for MIPS [d]mfc0 select 0 (except the count register), so that the coproc register is simply copied. The MIPS suspend instruction now exits the emulator, instead of being treated as a wait instruction (this causes NetBSD/ hpcmips to get correct 'halt' behavior). The VR41xx RTC now returns correct time. Connecting the VR41xx timer to the timer framework (fixed at 128 Hz, for now). Continuing on SPARC emulation, adding more instructions: restore, ba_xcc, ble. The rectangle drawing demo works :) Removing the last traces of the old ENABLE_CACHE_EMULATION MIPS stuff (not usable with dyntrans anyway). 20060902 Splitting up src/net.c into several smaller files in its own subdirectory (src/net/). 20060903 Cleanup of the files in src/net/, to make them less ugly. 20060904 Continuing on the 'settings' subsystem. Minor progress on the SPARC emulation mode. 20060905 Cleanup of various things, and connecting the settings infrastructure to various subsystems (emul, machine, cpu, etc). Changing the lk201 mouse update routine to not rely on any emulated hardware framebuffer cursor coordinates, but instead always do (semi-usable) relative movements. 20060906 Continuing on the lk201 mouse stuff. Mouse behaviour with multiple framebuffers (which was working in Ultrix) is now semi-broken (but it still works, in a way). Moving the documentation about networking into its own file (networking.html), and refreshing it a bit. Adding an example of how to use ethernet frame direct-access (udp_snoop). 20060907 Continuing on the settings infrastructure. 20060908 Minor updates to SH emulation: for 32-bit emulation: delay slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on ice, for now. 20060909-10 Implementing some more 32-bit SH instructions. Removing the 64-bit mode completely. Enough has now been implemented to run the rectangle drawing demo. :-) 20060912 Adding more SH instructions. 20060916 Continuing on SH emulation (some more instructions: div0u, div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett, tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac). Continuing on the settings subsystem (beginning on reading/ writing settings, removing bugs, and connecting more cpus to the framework). 20060919 More work on SH emulation; adding an ldc banked instruction, and attaching a 640x480 framebuffer to the Dreamcast machine mode (NetBSD/dreamcast prints the NetBSD copyright banner :-), and then panics). 20060920 Continuing on the settings subsystem. 20060921 Fixing the Footbridge timer stuff so that NetBSD/cats and NetBSD/netwinder boot up without the delays. 20060922 Temporarily hardcoding MIPS timer interrupt to 100 Hz. With 'wait' support disabled, NetBSD/malta and Linux/malta run at correct speed. 20060923 Connecting dev_gt to the timer framework, so that NetBSD/cobalt runs at correct speed. Moving SH4-specific memory mapped registers into its own device (dev_sh4.c). Running with -N now prints "idling" instead of bogus nr of instrs/second (which isn't valid anyway) while idling. 20060924 Algor emulation should now run at correct speed. Adding disassembly support for some MIPS64 revision 2 instructions: ext, dext, dextm, dextu. 20060926 The timer framework now works also when the MIPS wait instruction is used. 20060928 Re-implementing checks for coprocessor availability for MIPS cop0 instructions. (Thanks to Carl van Schaik for noticing the lack of cop0 availability checks.) 20060929 Implementing an instruction combination hack which treats NetBSD/pmax' idle loop as a wait-like instruction. 20060930 The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c, causing TLB lookups to sometimes succeed when they should have failed. (A big thank you to Juli Mallett for noticing the problem.) Adding disassembly support for more MIPS64 revision 2 opcodes (seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu, dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also implementing seb, seh, dsbh, dshd, and wsbh. Implementing an instruction combination hack for Linux/pmax' idle loop, similar to the NetBSD/pmax case. 20061001 Changing the NetBSD/sgimips install instructions to extract files from an iso image, instead of downloading them via ftp. 20061002 More-than-31-bit userland addresses in memory_mips_v2p.c were not actually working; applying a fix from Carl van Schaik to enable them to work + making some other updates (adding kuseg support). Fixing hpcmips (vr41xx) timer initialization. Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup loop. Seems to work both for R3000 and non-R3000. 20061003 Continuing a little on SH emulation (adding more control registers; mini-cleanup of memory_sh.c). 20061004 Beginning on a dev_rtc, a clock/timer device for the test machines; also adding a demo, and some documentation. Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't sign-extended), and adding the addc and ldtlb instructions. 20061005 Contining on SH emulation: virtual to physical address translation, and a skeleton exception mechanism. 20061006 Adding more SH instructions (various loads and stores, rte, negc, muls.w, various privileged register-move instructions). 20061007 More SH instructions: various move instructions, trapa, div0s, float, fdiv, ftrc. Continuing on dev_rtc; removing the rtc demo. 20061008 Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast programs using KOS libs need this.) Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca, fmul, fadd, various floating-point moves, etc. A 256-byte demo for Dreamcast runs :-) 20061012 Adding the SH "lds Rm,pr" and bsr instructions. 20061013 More SH instructions: "sts fpscr,rn", tas.b, and some more floating point instructions, cmp/str, and more moves. Adding a dummy dev_pvr (Dreamcast graphics controller). 20061014 Generalizing the expression evaluator (used in the built-in debugger) to support parentheses and +-*/%^&|. 20061015 Removing the experimental tlb index hint code in mips_memory_v2p.c, since it didn't really have any effect. 20061017 Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg, frchg, and some other instructions. Fixing missing sign- extension in an 8-bit load instruction. 20061019 Adding a simple dev_dreamcast_rtc. Implementing memory-mapped access to the SH ITLB/UTLB arrays. 20061021 Continuing on various SH and Dreamcast things: sh4 timers, debug messages for dev_pvr, fixing some virtual address translation bugs, adding the bsrf instruction. The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :) Adding a dummy dev_dreamcast_asic.c (not really useful yet). Implementing simple support for Store Queues. Beginning on the PVR Tile Accelerator. 20061022 Generalizing the PVR framebuffer to support off-screen drawing, multiple bit-depths, etc. (A small speed penalty, but most likely worth it.) Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac, fschg, and some more); correcting bugs in "fsca" and "float". 20061024 Adding the SH ftrv (matrix * vector) instruction. Marcus Comstedt's "tatest" example runs :) (wireframe only). Correcting disassembly for SH floating point instructions that use the xd* registers. Adding the SH fsts instruction. In memory_device_dyntrans_access(), only the currently used range is now invalidated, and not the entire device range. 20061025 Adding a dummy AVR32 cpu mode skeleton. 20061026 Various Dreamcast updates; beginning on a Maple bus controller. 20061027 Continuing on the Maple bus. A bogus Controller, Keyboard, and Mouse can now be detected by NetBSD and KOS homebrew programs. Cleaning up the SH4 Timer Management Unit, and beginning on SH4 interrupts. Implementing the Dreamcast SYSASIC. 20061028 Continuing on the SYSASIC. Adding the SH fsqrt instruction. memory_sh.c now actually scans the ITLB. Fixing a bug in dev_sh4.c, related to associative writes into the memory-mapped UTLB array. NetBSD/dreamcast now reaches userland stably, and prints the "Terminal type?" message :-] Implementing enough of the Dreamcast keyboard to make NetBSD accept it for input. Enabling SuperH for stable (non-development) builds. Adding NetBSD/dreamcast to the documentation, although it doesn't support root-on-nfs yet. 20061029 Changing usleep(1) calls in the debugger to to usleep(10000) (according to Brian Foley, this makes GXemul run better on MacOS X). Making the Maple "Controller" do something (enough to barely interact with dcircus.elf). 20061030-31 Some progress on the PVR. More test programs start running (but with strange output). Various other SH4-related updates. 20061102 Various Dreamcast and SH4 updates; more KOS demos run now. 20061104 Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter). 20061105 Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0. Testing for the release. ============== RELEASE 0.4.3 ==============
1 | #ifndef CPU_SPARC_H |
2 | #define CPU_SPARC_H |
3 | |
4 | /* |
5 | * Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions are met: |
9 | * |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
28 | * SUCH DAMAGE. |
29 | * |
30 | * |
31 | * $Id: cpu_sparc.h,v 1.42 2006/09/04 15:35:55 debug Exp $ |
32 | */ |
33 | |
34 | #include "misc.h" |
35 | |
36 | |
37 | struct cpu_family; |
38 | |
39 | |
40 | /* SPARC CPU types: */ |
41 | struct sparc_cpu_type_def { |
42 | char *name; |
43 | int v; /* v8, v9 etc */ |
44 | int bits; /* 32 or 64 */ |
45 | int nwindows; /* usually 8 or more */ |
46 | int icache_shift; |
47 | int ilinesize; |
48 | int iway; |
49 | int dcache_shift; |
50 | int dlinesize; |
51 | int dway; |
52 | int l2cache_shift; |
53 | int l2linesize; |
54 | int l2way; |
55 | }; |
56 | |
57 | /* NOTE/TODO: Maybe some of the types listed below as v8 are in |
58 | fact v7; I haven't had time to check. Also, the nwindows value is |
59 | just bogus. */ |
60 | /* See http://www.sparc.com/standards/v8v9-numbers.html for |
61 | implementation numbers! */ |
62 | |
63 | #define SPARC_CPU_TYPE_DEFS { \ |
64 | { "TMS390Z50", 8, 32, 8, 14,5,2, 14,5,2, 0,0,0 }, \ |
65 | { "MB86904", 8, 32, 8, 14,5,2, 13,4,2, 0,0,0 }, \ |
66 | { "MB86907", 8, 32, 8, 14,5,2, 14,5,2, 19,5,1 }, \ |
67 | { "UltraSPARC", 9, 64, 8, 14,5,4, 14,5,4, 19,6,1 }, \ |
68 | { "UltraSPARC-IIi", 9, 64, 8, 15,5,2, 14,5,2, 21,6,1 }, \ |
69 | { "UltraSPARC-II", 9, 64, 8, 15,5,2, 14,5,2, 22,6,1 }, \ |
70 | { NULL, 0, 0, 0, 0,0,0, 0,0,0, 0,0,0 } \ |
71 | } |
72 | |
73 | |
74 | #define SPARC_N_IC_ARGS 3 |
75 | #define SPARC_INSTR_ALIGNMENT_SHIFT 2 |
76 | #define SPARC_IC_ENTRIES_SHIFT 10 |
77 | #define SPARC_IC_ENTRIES_PER_PAGE (1 << SPARC_IC_ENTRIES_SHIFT) |
78 | #define SPARC_PC_TO_IC_ENTRY(a) (((a)>>SPARC_INSTR_ALIGNMENT_SHIFT) \ |
79 | & (SPARC_IC_ENTRIES_PER_PAGE-1)) |
80 | #define SPARC_ADDR_TO_PAGENR(a) ((a) >> (SPARC_IC_ENTRIES_SHIFT \ |
81 | + SPARC_INSTR_ALIGNMENT_SHIFT)) |
82 | |
83 | #define SPARC_L2N 17 |
84 | #define SPARC_L3N 18 /* 4KB pages on 32-bit sparc, */ |
85 | /* 8KB pages on 64-bit? TODO */ |
86 | |
87 | DYNTRANS_MISC_DECLARATIONS(sparc,SPARC,uint64_t) |
88 | DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC,uint8_t) |
89 | |
90 | #define SPARC_MAX_VPH_TLB_ENTRIES 128 |
91 | |
92 | |
93 | #define N_SPARC_REG 32 |
94 | #define N_SPARC_INOUT_REG 8 |
95 | #define N_SPARC_LOCAL_REG 8 |
96 | #define SPARC_REG_NAMES { \ |
97 | "g0","g1","g2","g3","g4","g5","g6","g7", \ |
98 | "o0","o1","o2","o3","o4","o5","sp","o7", \ |
99 | "l0","l1","l2","l3","l4","l5","l6","l7", \ |
100 | "i0","i1","i2","i3","i4","i5","fp","i7" } |
101 | |
102 | #define SPARC_ZEROREG 0 /* g0 */ |
103 | #define SPARC_REG_G0 0 |
104 | #define SPARC_REG_G1 1 |
105 | #define SPARC_REG_G2 2 |
106 | #define SPARC_REG_G3 3 |
107 | #define SPARC_REG_G4 4 |
108 | #define SPARC_REG_G5 5 |
109 | #define SPARC_REG_G6 6 |
110 | #define SPARC_REG_G7 7 |
111 | #define SPARC_REG_O0 8 |
112 | #define SPARC_REG_O1 9 |
113 | #define SPARC_REG_O2 10 |
114 | #define SPARC_REG_O3 11 |
115 | #define SPARC_REG_O4 12 |
116 | #define SPARC_REG_O5 13 |
117 | #define SPARC_REG_O6 14 |
118 | #define SPARC_REG_O7 15 |
119 | #define SPARC_REG_L0 16 |
120 | #define SPARC_REG_L1 17 |
121 | #define SPARC_REG_L2 18 |
122 | #define SPARC_REG_L3 19 |
123 | #define SPARC_REG_L4 20 |
124 | #define SPARC_REG_L5 21 |
125 | #define SPARC_REG_L6 22 |
126 | #define SPARC_REG_L7 23 |
127 | #define SPARC_REG_I0 24 |
128 | #define SPARC_REG_I1 25 |
129 | #define SPARC_REG_I2 26 |
130 | #define SPARC_REG_I3 27 |
131 | #define SPARC_REG_I4 28 |
132 | #define SPARC_REG_I5 29 |
133 | #define SPARC_REG_I6 30 |
134 | #define SPARC_REG_I7 31 |
135 | |
136 | /* Privileged registers: */ |
137 | #define N_SPARC_PREG 32 |
138 | #define SPARC_PREG_NAMES { \ |
139 | "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", \ |
140 | "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", \ |
141 | "wstate", "fq", "reserved16", "reserved17", "reserved18", \ |
142 | "reserved19", "reserved20", "reserved21", "reserved22", \ |
143 | "reserved23", "reserved24", "reserved25", "reserved26", \ |
144 | "reserved27", "reserved28", "reserved29", "reserved30", \ |
145 | "ver" } |
146 | |
147 | #define N_SPARC_BRANCH_TYPES 16 |
148 | #define SPARC_BRANCH_NAMES { \ |
149 | "bn", "be", "ble", "bl", "bleu", "bcs", "bneg", "bvs", \ |
150 | "ba", "bne", "bg", "bge", "bgu", "bcc", "bpos", "bvc" } |
151 | |
152 | #define N_SPARC_REGBRANCH_TYPES 8 |
153 | #define SPARC_REGBRANCH_NAMES { \ |
154 | "br?","brz","brlez","brlz","br??","brnz", "brgz", "brgez" } |
155 | |
156 | #define N_ALU_INSTR_TYPES 64 |
157 | #define SPARC_ALU_NAMES { \ |
158 | "add", "and", "or", "xor", "sub", "andn", "orn", "xnor", \ |
159 | "addx", "[9]", "umul", "smul", "subx", "[13]", "udiv", "sdiv", \ |
160 | "addcc","andcc","orcc","xorcc","subcc","andncc","orncc","xnorcc",\ |
161 | "addxcc","[25]","umulcc","smulcc","subxcc","[29]","udivcc","sdivcc",\ |
162 | "taddcc","tsubcc","taddcctv","tsubcctv","mulscc","sll","srl","sra",\ |
163 | "rd" /* membar/stbar on sparcv9 */, \ |
164 | "rd" /* rd psr on pre-sparcv9 */, "rdpr","rd", \ |
165 | "[44]","[45]","popc","movre", \ |
166 | "wr*","saved/restored","wrpr","[51]", "[52]","[53]","[54]","[55]",\ |
167 | "jmpl", "rett", "trap", "flush", "save", "restore", "[62]","[63]" } |
168 | |
169 | #define N_LOADSTORE_TYPES 64 |
170 | #define SPARC_LOADSTORE_NAMES { \ |
171 | "lduw","ldub","lduh","ldd", "st","stb","sth","std", \ |
172 | "ldsw","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap", \ |
173 | "lda","lduba","lduha","ldda", "sta","stba","stha","stda", \ |
174 | "[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa", \ |
175 | "ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf", \ |
176 | "[40]","[41]","[42]","[43]", "[44]","prefetch","[46]","[47]", \ |
177 | "ldc","ldcsr","[50]","lddc", "stc","stcsr","scdfq","scdf", \ |
178 | "[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" } |
179 | |
180 | |
181 | /* Max number of Trap Levels and Windows: */ |
182 | #define MAXTL 4 |
183 | #define MAXWIN 32 |
184 | |
185 | |
186 | struct sparc_cpu { |
187 | struct sparc_cpu_type_def cpu_type; |
188 | |
189 | /* Registers in the Current Window: */ |
190 | uint64_t r[N_SPARC_REG]; |
191 | |
192 | uint64_t r_inout[MAXWIN][N_SPARC_INOUT_REG]; |
193 | uint64_t r_local[MAXWIN][N_SPARC_LOCAL_REG]; |
194 | |
195 | uint64_t scratch; |
196 | |
197 | /* Pre-SPARCv9 specific: */ |
198 | uint32_t psr; /* Processor State Register */ |
199 | uint32_t tbr; /* Trap base register */ |
200 | uint32_t wim; /* Window invalid mask */ |
201 | |
202 | /* SPARCv9 etc.: */ |
203 | uint64_t pstate; /* Processor State Register */ |
204 | uint64_t y; /* Y-reg (only low 32-bits used) */ |
205 | uint64_t fprs; /* Floating Point Register Status */ |
206 | uint64_t tick; /* Tick Register */ |
207 | uint64_t tick_cmpr; /* Tick Compare Register (?) */ |
208 | uint64_t ver; /* Version register */ |
209 | |
210 | uint8_t cwp; /* Current Window Pointer */ |
211 | uint8_t cansave; /* CANSAVE register */ |
212 | uint8_t canrestore; /* CANRESTORE register */ |
213 | uint8_t otherwin; /* OTHERWIN register */ |
214 | uint8_t cleanwin; /* CLEANWIN register */ |
215 | |
216 | uint8_t wstate; /* Window state */ |
217 | |
218 | uint8_t ccr; /* Condition Code Register */ |
219 | uint8_t asi; /* Address Space Identifier */ |
220 | uint8_t tl; /* Trap Level Register */ |
221 | uint8_t pil; /* Processor Interrupt Level Reg. */ |
222 | |
223 | uint64_t tpc[MAXTL]; /* Trap Program Counter */ |
224 | uint64_t tnpc[MAXTL]; /* Trap Next Program Counter */ |
225 | uint64_t tstate[MAXTL]; /* Trap State */ |
226 | uint32_t ttype[MAXTL]; /* Trap Type */ |
227 | |
228 | uint64_t tba; /* Trap Base Address */ |
229 | |
230 | /* |
231 | * Instruction translation cache and Virtual->Physical->Host |
232 | * address translation: |
233 | */ |
234 | DYNTRANS_ITC(sparc) |
235 | VPH_TLBS(sparc,SPARC) |
236 | VPH32(sparc,SPARC,uint64_t,uint8_t) |
237 | VPH64(sparc,SPARC,uint8_t) |
238 | }; |
239 | |
240 | |
241 | /* Processor State Register (PSTATE) bit definitions: */ |
242 | #define SPARC_PSTATE_PID1 0x800 |
243 | #define SPARC_PSTATE_PID0 0x400 |
244 | #define SPARC_PSTATE_CLE 0x200 /* Current Little Endian */ |
245 | #define SPARC_PSTATE_TLE 0x100 /* Trap Little Endian */ |
246 | #define SPARC_PSTATE_MM_MASK 0x0c0 /* Memory Model (TODO) */ |
247 | #define SPARC_PSTATE_MM_SHIFT 6 |
248 | #define SPARC_PSTATE_RED 0x020 /* Reset/Error/Debug state */ |
249 | #define SPARC_PSTATE_PEF 0x010 /* Enable Floating-point */ |
250 | #define SPARC_PSTATE_AM 0x008 /* Address Mask */ |
251 | #define SPARC_PSTATE_PRIV 0x004 /* Privileged Mode */ |
252 | #define SPARC_PSTATE_IE 0x002 /* Interrupt Enable */ |
253 | #define SPARC_PSTATE_AG 0x001 /* Alternate Globals */ |
254 | |
255 | |
256 | /* Condition Code Register bit definitions: */ |
257 | #define SPARC_CCR_XCC_MASK 0xf0 |
258 | #define SPARC_CCR_XCC_SHIFT 4 |
259 | #define SPARC_CCR_ICC_MASK 0x0f |
260 | #define SPARC_CCR_N 8 |
261 | #define SPARC_CCR_Z 4 |
262 | #define SPARC_CCR_V 2 |
263 | #define SPARC_CCR_C 1 |
264 | |
265 | |
266 | /* CWP, CANSAVE, CANRESTORE, OTHERWIN, CLEANWIN bitmask: */ |
267 | #define SPARC_CWP_MASK 0x1f |
268 | |
269 | |
270 | /* Window State bit definitions: */ |
271 | #define SPARC_WSTATE_OTHER_MASK 0x38 |
272 | #define SPARC_WSTATE_OTHER_SHIFT 3 |
273 | #define SPARC_WSTATE_NORMAL_MASK 0x07 |
274 | |
275 | |
276 | /* Tick Register bit definitions: */ |
277 | #define SPARC_TICK_NPT (1ULL << 63) /* Non-privileged trap */ |
278 | |
279 | |
280 | /* Addess Space Identifier bit definitions: */ |
281 | #define SPARC_ASI_RESTRICTED 0x80 |
282 | |
283 | |
284 | /* Trap Level Register bit definitions: */ |
285 | #define SPARC_TL_MASK 0x07 |
286 | |
287 | |
288 | /* Processor Interrupt Level Register bit definitions: */ |
289 | #define SPARC_PIL_MASK 0x0f |
290 | |
291 | |
292 | /* Trap Type Register bit definitions: */ |
293 | #define SPARC_TTYPE_MASK 0x1ff |
294 | |
295 | |
296 | /* Trap Base Address bit definitions: */ |
297 | #define SPARC_TBA_MASK 0xffffffffffff8000ULL |
298 | |
299 | |
300 | /* |
301 | * Full address for a trap is: |
302 | * TBA<bits 63..15> || X || TTYPE[TL] || 00000 |
303 | * |
304 | * where X is a bit which is true if TL>0 when the trap was taken. |
305 | */ |
306 | |
307 | |
308 | /* Version Register bit definitions: */ |
309 | #define SPARC_VER_MANUF_SHIFT 48 |
310 | #define SPARC_VER_IMPL_SHIFT 32 |
311 | #define SPARC_VER_MASK_SHIFT 24 |
312 | #define SPARC_VER_MAXTL_SHIFT 8 |
313 | #define SPARC_VER_MAXWIN_SHIFT 0 |
314 | |
315 | |
316 | /* cpu_sparc.c: */ |
317 | int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
318 | int sparc_run_instr(struct cpu *cpu); |
319 | void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
320 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
321 | void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
322 | void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
323 | int sparc32_run_instr(struct cpu *cpu); |
324 | void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
325 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
326 | void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
327 | void sparc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
328 | void sparc_init_64bit_dummy_tables(struct cpu *cpu); |
329 | int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
330 | unsigned char *data, size_t len, int writeflag, int cache_flags); |
331 | int sparc_cpu_family_init(struct cpu_family *); |
332 | |
333 | /* memory_sparc.c: */ |
334 | int sparc_translate_v2p(struct cpu *cpu, uint64_t vaddr, |
335 | uint64_t *return_addr, int flags); |
336 | |
337 | |
338 | #endif /* CPU_SPARC_H */ |
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