Parent Directory | Revision Log
++ trunk/HISTORY (local) $Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $ 20060219 Various minor updates. Removing the old MIPS16 skeleton code, because it will need to be rewritten for dyntrans anyway. 20060220-22 Removing the non-working dyntrans backend support. Continuing on the 64-bit dyntrans virtual memory generalization. 20060223 More work on the 64-bit vm generalization. 20060225 Beginning on MIPS dyntrans load/store instructions. Minor PPC updates (64-bit load/store, etc). Fixes for the variable-instruction-length framework, some minor AVR updates (a simple Hello World program works!). Beginning on a skeleton for automatically generating documen- tation (for devices etc.). 20060226 PPC updates (adding some more 64-bit instructions, etc). AVR updates (more instructions). FINALLY found and fixed the zs bug, making NetBSD/macppc accept the serial console. 20060301 Adding more AVR instructions. 20060304 Continuing on AVR-related stuff. Beginning on a framework for cycle-accurate device emulation. Adding an experimental "PAL TV" device (just a dummy so far). 20060305 Adding more AVR instructions. Adding a dummy epcom serial controller (for TS7200 emulation). 20060310 Removing the emul() command from configuration files, so only net() and machine() are supported. Minor progress on the MIPS dyntrans rewrite. 20060311 Continuing on the MIPS dyntrans rewrite (adding more instructions, etc). 20060315 Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l], beql, bnel, slti[u], various loads and stores). 20060316 Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely used. Adding more MIPS dyntrans instructions, and fixing bugs. 20060318 Implementing fast loads/stores for MIPS dyntrans (big/little endian, 32-bit and 64-bit modes). 20060320 Making MIPS dyntrans the default configure option; use "--enable-oldmips" to use the old bintrans system. Adding MIPS dyntrans dmult[u]; minor updates. 20060322 Continuing... adding some more instructions. Adding a simple skeleton for demangling C++ "_ZN" symbols. 20060323 Moving src/debugger.c into a new directory (src/debugger/). 20060324 Fixing the hack used to load PPC ELFs (useful for relocated Linux/ppc kernels), and adding a dummy G3 machine mode. 20060325-26 Beginning to experiment with GDB remote serial protocol connections; adding a -G command line option for selecting which TCP port to listen to. 20060330 Beginning a major cleanup to replace things like "0x%016llx" with more correct "0x%016"PRIx64, etc. Continuing on the GDB remote serial protocol support. 20060331 More cleanup, and some minor GDB remote progress. 20060402 Adding a hack to the configure script, to allow compilation on systems that lack PRIx64 etc. 20060406 Removing the temporary FreeBSD/arm hack in dev_ns16550.c and replacing it with a better fix from Olivier Houchard. 20060407 A remote debugger (gdb or ddd) can now start and stop the emulator using the GDB remote serial protocol, and registers and memory can be read. MIPS only for now. 20060408 More GDB progress: single-stepping also works, and also adding support for ARM, PowerPC, and Alpha targets. Continuing on the delay-slot-across-page-boundary issue. 20060412 Minor update: beginning to add support for the SPARC target to the remote GDB functionality. 20060414 Various MIPS updates: adding more instructions for dyntrans (eret, add), and making some exceptions work. Fixing a bug in dmult[u]. Implementing the first SPARC instructions (sethi, or). 20060415 Adding "magic trap" instructions so that PROM calls can be software emulated in MIPS dyntrans. Adding more MIPS dyntrans instructions (ddiv, dadd) and fixing another bug in dmult. 20060416 More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv, rfi, an ugly hack for supporting R2000/R3000 style faked caches, preliminary interrupt support, and various other updates and bugfixes. 20060417 Adding more SPARC instructions (add, sub, sll[x], sra[x], srl[x]), and useful SPARC header definitions. Adding the first (trivial) x86/AMD64 dyntrans instructions (nop, cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other x86 updates related to variable instruction length stuff. Adding unaligned loads/stores to the MIPS dyntrans mode (but still using the pre-dyntrans (slow) imlementation). 20060419 Fixing a MIPS dyntrans exception-in-delay-slot bug. Removing the old "show opcode statistics" functionality, since it wasn't really useful and isn't implemented for dyntrans. Single-stepping (or running with instruction trace) now looks ok with dyntrans with delay-slot architectures. 20060420 Minor hacks (removing the -B command line option when compiled for non-bintrans, and some other very minor updates). Adding (slow) MIPS dyntrans load-linked/store-conditional. 20060422 Applying fixes for bugs discovered by Nils Weller's nwcc (static DEC memmap => now per machine, and adding an extern keyword in cpu_arm_instr.c). Finally found one of the MIPS dyntrans bugs that I've been looking for (copy/paste spelling error BIG vs LITTLE endian in cpu_mips_instr_loadstore.c for 16-bit fast stores). FINALLY found the major MIPS dyntrans bug: slti vs sltiu signed/unsigned code in cpu_mips_instr.c. :-) Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l], ctc1, tlt[u], tge[u], tne, beginning on rdhwr). NetBSD/hpcmips can now reach userland when using dyntrans :-) Adding some more x86 dyntrans instructions. Finally removed the old Alpha-specific virtual memory code, and replaced it with the generic 64-bit version. Beginning to add disassembly support for SPECIAL3 MIPS opcodes. 20060423 Continuing on the delay-slot-across-page-boundary issue; adding an end_of_page2 ic slot (like I had planned before, but had removed for some reason). Adding a quick-and-dirty fallback to legacy coprocessor 1 code (i.e. skipping dyntrans implementation for now). NetBSD/hpcmips and NetBSD/pmax (when running on an emulated R4400) can now be installed and run. :-) (Many bugs left to fix, though.) Adding more MIPS dyntrans instructions: madd[u], msub[u]. Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode maps somewhat (disassembly and dyntrans instruction decoding). 20060424 Adding an isa_revision field to mips_cpu_types.h, and making sure that SPECIAL3 opcodes cause Reserved Instruction exceptions on MIPS32/64 revisions lower than 2. Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor' instructions. 20060425 Removing the -m command line option ("run at most x instructions") and -T ("single_step_on_bad_addr"), because they never worked correctly with dyntrans anyway. Freshening up the man page. 20060428 Adding more MIPS dyntrans instructions: bltzal[l], idle. Enabling MIPS dyntrans compare interrupts. 20060429 FINALLY found the weird dyntrans bug, causing NetBSD etc. to behave strangely: some floating point code (conditional coprocessor branches) could not be reused from the old non-dyntrans code. The "quick-and-dirty fallback" only appeared to work. Fixing by implementing bc1* for MIPS dyntrans. More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0. Freshening up MIPS floating point disassembly appearance. 20060430 Continuing on C790/R5900/TX79 disassembly; implementing 128-bit "por" and "pextlw". 20060504 Disabling -u (userland emulation) unless compiled as unstable development version. Beginning on freshening up the testmachine include files, to make it easier to reuse those files (placing them in src/include/testmachine/), and beginning on a set of "demos" or "tutorials" for the testmachine functionality. Minor updates to the MIPS GDB remote protocol stub. Refreshing doc/experiments.html and gdb_remote.html. Enabling Alpha emulation in the stable release configuration, even though no guest OSes for Alpha can run yet. 20060505 Adding a generic 'settings' object, which will contain references to settable variables (which will later be possible to access using the debugger). 20060506 Updating dev_disk and corresponding demo/documentation (and switching from SCSI to IDE disk types, so it actually works with current test machines :-). 20060510 Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts, so that fseeko() doesn't give a warning. Updating the section about how dyntrans works (the "runnable IR") in doc/intro.html. Instruction updates (some x64=1 checks, some more R5900 dyntrans stuff: better mul/mult separation from MIPS32/64, adding ei and di). Updating MIPS cpuregs.h to a newer one (from NetBSD). Adding more MIPS dyntrans instructions: deret, ehb. 20060514 Adding disassembly and beginning implementation of SPARC wr and wrpr instructions. 20060515 Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1 machines. Adding the 32-bit "rd psr" instruction. 20060517 Disassembly support for the general SPARC rd instruction. Partial implementation of the cmp (subcc) instruction. Some other minor updates (making sure that R5900 processors start up with the EIE bit enabled, otherwise Linux/playstation2 receives no interrupts). 20060519 Minor MIPS updates/cleanups. 20060521 Moving the MeshCube machine into evbmips; this seems to work reasonably well with a snapshot of a NetBSD MeshCube kernel. Cleanup/fix of MIPS config0 register initialization. 20060529 Minor MIPS fixes, including a sign-extension fix to the unaligned load/store code, which makes NetBSD/pmax on R3000 work better with dyntrans. (Ultrix and Linux/DECstation still don't work, though.) 20060530 Minor updates to the Alpha machine mode: adding an AlphaBook mode, an LCA bus (forwarding accesses to an ISA bus), etc. 20060531 Applying a bugfix for the MIPS dyntrans sc[d] instruction from Ondrej Palkovsky. (Many thanks.) 20060601 Minifix to allow ARM immediate msr instruction to not give an error for some valid values. More Alpha updates. 20060602 Some minor Alpha updates. 20060603 Adding the Alpha cmpbge instruction. NetBSD/alpha prints its first boot messages :-) on an emulated Alphabook 1. 20060612 Minor updates; adding a dev_ether.h include file for the testmachine ether device. Continuing the hunt for the dyntrans bug which makes Linux and Ultrix on DECstation behave strangely... FINALLY found it! It seems to be related to invalidation of the translation cache, on tlbw{r,i}. There also seems to be some remaining interrupt-related problems. 20060614 Correcting the implementation of ldc1/sdc1 for MIPS dyntrans (so that it uses 16 32-bit registers if the FR bit in the status register is not set). 20060616 REMOVING BINTRANS COMPLETELY! Removing the old MIPS interpretation mode. Removing the MFHILO_DELAY and instruction delay stuff, because they wouldn't work with dyntrans anyway. 20060617 Some documentation updates (adding "NetBSD-archive" to some URLs, and new Debian/DECstation installation screenshots). Removing the "tracenull" and "enable-caches" configure options. Improving MIPS dyntrans performance somewhat (only invalidate translations if necessary, on writes to the entryhi register, instead of doing it for all cop0 writes). 20060618 More cleanup after the removal of the old MIPS emulation. Trying to fix the MIPS dyntrans performance bugs/bottlenecks; only semi-successful so far (for R3000). 20060620 Minor update to allow clean compilation again on Tru64/Alpha. 20060622 MIPS cleanup and fixes (removing the pc_last stuff, which doesn't make sense with dyntrans anyway, and fixing a cross- page-delay-slot-with-exception case in end_of_page). Removing the old max_random_cycles_per_chunk stuff, and the concept of cycles vs instructions for MIPS emulation. FINALLY found and fixed the bug which caused NetBSD/pmax clocks to behave strangely (it was a load to the zero register, which was treated as a NOP; now it is treated as a load to a dummy scratch register). 20060623 Increasing the dyntrans chunk size back to N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2. Preparing for a quick release, even though there are known bugs, and performance for non-R3000 MIPS emulation is very poor. :-/ Reverting to half the dyntrans chunk size again, because NetBSD/cats seemed less stable with full size chunks. :( NetBSD/sgimips 3.0 can now run :-) (With release 0.3.8, only NetBSD/sgimips 2.1 worked, not 3.0.) ============== RELEASE 0.4.0 ==============
1 | dpavlin | 12 | #ifndef CPU_SPARC_H |
2 | #define CPU_SPARC_H | ||
3 | |||
4 | /* | ||
5 | dpavlin | 22 | * Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
6 | dpavlin | 12 | * |
7 | * Redistribution and use in source and binary forms, with or without | ||
8 | * modification, are permitted provided that the following conditions are met: | ||
9 | * | ||
10 | * 1. Redistributions of source code must retain the above copyright | ||
11 | * notice, this list of conditions and the following disclaimer. | ||
12 | * 2. Redistributions in binary form must reproduce the above copyright | ||
13 | * notice, this list of conditions and the following disclaimer in the | ||
14 | * documentation and/or other materials provided with the distribution. | ||
15 | * 3. The name of the author may not be used to endorse or promote products | ||
16 | * derived from this software without specific prior written permission. | ||
17 | * | ||
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | ||
19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | ||
22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | ||
23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | ||
24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | ||
25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | ||
26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | ||
27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | ||
28 | * SUCH DAMAGE. | ||
29 | * | ||
30 | * | ||
31 | dpavlin | 24 | * $Id: cpu_sparc.h,v 1.38 2006/05/18 05:10:44 debug Exp $ |
32 | dpavlin | 12 | */ |
33 | |||
34 | #include "misc.h" | ||
35 | |||
36 | |||
37 | struct cpu_family; | ||
38 | |||
39 | |||
40 | dpavlin | 22 | /* SPARC CPU types: */ |
41 | struct sparc_cpu_type_def { | ||
42 | char *name; | ||
43 | int bits; | ||
44 | int icache_shift; | ||
45 | int ilinesize; | ||
46 | int iway; | ||
47 | int dcache_shift; | ||
48 | int dlinesize; | ||
49 | int dway; | ||
50 | int l2cache_shift; | ||
51 | int l2linesize; | ||
52 | int l2way; | ||
53 | }; | ||
54 | |||
55 | #define SPARC_CPU_TYPE_DEFS { \ | ||
56 | dpavlin | 24 | { "TMS390Z50", 32, 14,5,2, 14,5,2, 0,0,0 }, \ |
57 | { "MB86904", 32, 14,5,2, 13,4,2, 0,0,0 }, \ | ||
58 | { "MB86907", 32, 14,5,2, 14,5,2, 19,5,1 }, \ | ||
59 | { "UltraSPARC", 64, 14,5,4, 14,5,4, 19,6,1 }, \ | ||
60 | { "UltraSPARC-IIi", 64, 15,5,2, 14,5,2, 21,6,1 }, \ | ||
61 | { "UltraSPARC-II", 64, 15,5,2, 14,5,2, 22,6,1 }, \ | ||
62 | { NULL, 0, 0,0,0, 0,0,0, 0,0,0 } \ | ||
63 | dpavlin | 22 | } |
64 | |||
65 | |||
66 | dpavlin | 12 | #define SPARC_N_IC_ARGS 3 |
67 | #define SPARC_INSTR_ALIGNMENT_SHIFT 2 | ||
68 | #define SPARC_IC_ENTRIES_SHIFT 10 | ||
69 | #define SPARC_IC_ENTRIES_PER_PAGE (1 << SPARC_IC_ENTRIES_SHIFT) | ||
70 | #define SPARC_PC_TO_IC_ENTRY(a) (((a)>>SPARC_INSTR_ALIGNMENT_SHIFT) \ | ||
71 | & (SPARC_IC_ENTRIES_PER_PAGE-1)) | ||
72 | #define SPARC_ADDR_TO_PAGENR(a) ((a) >> (SPARC_IC_ENTRIES_SHIFT \ | ||
73 | + SPARC_INSTR_ALIGNMENT_SHIFT)) | ||
74 | |||
75 | dpavlin | 24 | #define SPARC_L2N 17 |
76 | #define SPARC_L3N 18 /* 4KB pages on 32-bit sparc, */ | ||
77 | /* 8KB pages on 64-bit? TODO */ | ||
78 | |||
79 | dpavlin | 22 | DYNTRANS_MISC_DECLARATIONS(sparc,SPARC,uint64_t) |
80 | dpavlin | 24 | DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC,uint8_t) |
81 | dpavlin | 12 | |
82 | dpavlin | 22 | #define SPARC_MAX_VPH_TLB_ENTRIES 128 |
83 | dpavlin | 12 | |
84 | |||
85 | dpavlin | 22 | #define N_SPARC_REG 32 |
86 | #define SPARC_REG_NAMES { \ | ||
87 | "g0","g1","g2","g3","g4","g5","g6","g7", \ | ||
88 | "o0","o1","o2","o3","o4","o5","sp","o7", \ | ||
89 | "l0","l1","l2","l3","l4","l5","l6","l7", \ | ||
90 | "i0","i1","i2","i3","i4","i5","fp","i7" } | ||
91 | dpavlin | 12 | |
92 | dpavlin | 24 | #define SPARC_ZEROREG 0 /* g0 */ |
93 | #define SPARC_REG_G0 0 | ||
94 | #define SPARC_REG_G1 1 | ||
95 | #define SPARC_REG_G2 2 | ||
96 | #define SPARC_REG_G3 3 | ||
97 | #define SPARC_REG_G4 4 | ||
98 | #define SPARC_REG_G5 5 | ||
99 | #define SPARC_REG_G6 6 | ||
100 | #define SPARC_REG_G7 7 | ||
101 | #define SPARC_REG_O0 8 | ||
102 | #define SPARC_REG_O1 9 | ||
103 | #define SPARC_REG_O2 10 | ||
104 | #define SPARC_REG_O3 11 | ||
105 | #define SPARC_REG_O4 12 | ||
106 | #define SPARC_REG_O5 13 | ||
107 | #define SPARC_REG_O6 14 | ||
108 | #define SPARC_REG_O7 15 | ||
109 | #define SPARC_REG_L0 16 | ||
110 | #define SPARC_REG_L1 17 | ||
111 | #define SPARC_REG_L2 18 | ||
112 | #define SPARC_REG_L3 19 | ||
113 | #define SPARC_REG_L4 20 | ||
114 | #define SPARC_REG_L5 21 | ||
115 | #define SPARC_REG_L6 22 | ||
116 | #define SPARC_REG_L7 23 | ||
117 | #define SPARC_REG_I0 24 | ||
118 | #define SPARC_REG_I1 25 | ||
119 | #define SPARC_REG_I2 26 | ||
120 | #define SPARC_REG_I3 27 | ||
121 | #define SPARC_REG_I4 28 | ||
122 | #define SPARC_REG_I5 29 | ||
123 | #define SPARC_REG_I6 30 | ||
124 | #define SPARC_REG_I7 31 | ||
125 | |||
126 | /* Privileged registers: */ | ||
127 | #define N_SPARC_PREG 32 | ||
128 | #define SPARC_PREG_NAMES { \ | ||
129 | "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", \ | ||
130 | "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", \ | ||
131 | "wstate", "reserved15", "reserved16", "reserved17", "reserved18", \ | ||
132 | "reserved19", "reserved20", "reserved21", "reserved22", \ | ||
133 | "reserved23", "reserved24", "reserved25", "reserved26", \ | ||
134 | "reserved27", "reserved28", "reserved29", "reserved30", \ | ||
135 | "reserved31" } | ||
136 | |||
137 | dpavlin | 22 | #define N_SPARC_BRANCH_TYPES 16 |
138 | #define SPARC_BRANCH_NAMES { \ | ||
139 | "bn", "be", "ble", "bl", "bleu", "bcs", "bneg", "bvs", \ | ||
140 | dpavlin | 24 | "ba", "bne", "bg", "bge", "bgu", "bcc", "bpos", "bvc" } |
141 | dpavlin | 12 | |
142 | dpavlin | 22 | #define N_SPARC_REGBRANCH_TYPES 8 |
143 | #define SPARC_REGBRANCH_NAMES { \ | ||
144 | "br?","brz","brlez","brlz","br??","brnz", "brgz", "brgez" } | ||
145 | dpavlin | 12 | |
146 | dpavlin | 22 | #define N_ALU_INSTR_TYPES 64 |
147 | #define SPARC_ALU_NAMES { \ | ||
148 | "add", "and", "or", "xor", "sub", "andn", "orn", "xnor", \ | ||
149 | "addx", "[9]", "umul", "smul", "subx", "[13]", "udiv", "sdiv", \ | ||
150 | "addcc","andcc","orcc","xorcc","subcc","andncc","orncc","xnorcc",\ | ||
151 | "addxcc","[25]","umulcc","smulcc","subxcc","[29]","udivcc","sdivcc",\ | ||
152 | "taddcc","tsubcc","taddcctv","tsubcctv","mulscc","sll","srl","sra",\ | ||
153 | dpavlin | 24 | "rd" /* membar/stbar on sparcv9 */, \ |
154 | "rd" /* rd psr on pre-sparcv9 */, "rdpr","rd", \ | ||
155 | "[44]","[45]","popc","movre", \ | ||
156 | "wr*","saved/restored","wrpr","[51]", "[52]","[53]","[54]","[55]",\ | ||
157 | dpavlin | 22 | "jmpl", "rett", "trap", "flush", "save", "restore", "[62]","[63]" } |
158 | dpavlin | 12 | |
159 | dpavlin | 22 | #define N_LOADSTORE_TYPES 64 |
160 | #define SPARC_LOADSTORE_NAMES { \ | ||
161 | "ld","ldub","lduh","ldd", "st","stb","sth","std", \ | ||
162 | "[8]","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap", \ | ||
163 | "lda","lduba","lduha","ldda", "sta","stba","stha","stda", \ | ||
164 | "[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa", \ | ||
165 | "ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf", \ | ||
166 | dpavlin | 24 | "[40]","[41]","[42]","[43]", "[44]","prefetch","[46]","[47]", \ |
167 | dpavlin | 22 | "ldc","ldcsr","[50]","lddc", "stc","stcsr","scdfq","scdf", \ |
168 | dpavlin | 24 | "[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" } |
169 | dpavlin | 12 | |
170 | dpavlin | 24 | |
171 | /* Max number of Trap Levels and Windows: */ | ||
172 | #define MAXTL 4 | ||
173 | #define MAXWIN 32 | ||
174 | |||
175 | |||
176 | dpavlin | 22 | struct sparc_cpu { |
177 | struct sparc_cpu_type_def cpu_type; | ||
178 | dpavlin | 12 | |
179 | dpavlin | 24 | /* Registers in the Current Window: */ |
180 | dpavlin | 22 | uint64_t r[N_SPARC_REG]; |
181 | |||
182 | dpavlin | 24 | uint64_t scratch; |
183 | dpavlin | 22 | |
184 | dpavlin | 24 | /* Pre-SPARCv9 specific: */ |
185 | uint32_t psr; /* Processor State Register */ | ||
186 | uint32_t tbr; /* Trap base register */ | ||
187 | uint32_t wim; /* Window invalid mask */ | ||
188 | |||
189 | /* SPARCv9 etc.: */ | ||
190 | uint64_t pstate; /* Processor State Register */ | ||
191 | uint64_t y; /* Y-reg (only low 32-bits used) */ | ||
192 | uint64_t fprs; /* Floating Point Register Status */ | ||
193 | uint64_t tick; /* Tick Register */ | ||
194 | uint64_t tick_cmpr; /* Tick Compare Register (?) */ | ||
195 | uint64_t ver; /* Version register */ | ||
196 | |||
197 | uint8_t cwp; /* Current Window Pointer */ | ||
198 | uint8_t cansave; /* CANSAVE register */ | ||
199 | uint8_t canrestore; /* CANRESTORE register */ | ||
200 | uint8_t otherwin; /* OTHERWIN register */ | ||
201 | uint8_t cleanwin; /* CLEANWIN register */ | ||
202 | |||
203 | uint8_t wstate; /* Window state */ | ||
204 | |||
205 | uint8_t ccr; /* Condition Code Register */ | ||
206 | uint8_t asi; /* Address Space Identifier */ | ||
207 | uint8_t tl; /* Trap Level Register */ | ||
208 | uint8_t pil; /* Processor Interrupt Level Reg. */ | ||
209 | |||
210 | uint64_t tpc[MAXTL]; /* Trap Program Counter */ | ||
211 | uint64_t tnpc[MAXTL]; /* Trap Next Program Counter */ | ||
212 | uint64_t tstate[MAXTL]; /* Trap State */ | ||
213 | uint32_t ttype[MAXTL]; /* Trap Type */ | ||
214 | |||
215 | uint64_t tba; /* Trap Base Address */ | ||
216 | |||
217 | dpavlin | 12 | /* |
218 | dpavlin | 22 | * Instruction translation cache and Virtual->Physical->Host |
219 | * address translation: | ||
220 | dpavlin | 12 | */ |
221 | dpavlin | 22 | DYNTRANS_ITC(sparc) |
222 | VPH_TLBS(sparc,SPARC) | ||
223 | VPH32(sparc,SPARC,uint64_t,uint8_t) | ||
224 | VPH64(sparc,SPARC,uint8_t) | ||
225 | dpavlin | 12 | }; |
226 | |||
227 | |||
228 | dpavlin | 24 | /* Processor State Register (PSTATE) bit definitions: */ |
229 | #define SPARC_PSTATE_PID1 0x800 | ||
230 | #define SPARC_PSTATE_PID0 0x400 | ||
231 | #define SPARC_PSTATE_CLE 0x200 /* Current Little Endian */ | ||
232 | #define SPARC_PSTATE_TLE 0x100 /* Trap Little Endian */ | ||
233 | #define SPARC_PSTATE_MM_MASK 0x0c0 /* Memory Model (TODO) */ | ||
234 | #define SPARC_PSTATE_MM_SHIFT 6 | ||
235 | #define SPARC_PSTATE_RED 0x020 /* Reset/Error/Debug state */ | ||
236 | #define SPARC_PSTATE_PEF 0x010 /* Enable Floating-point */ | ||
237 | #define SPARC_PSTATE_AM 0x008 /* Address Mask */ | ||
238 | #define SPARC_PSTATE_PRIV 0x004 /* Privileged Mode */ | ||
239 | #define SPARC_PSTATE_IE 0x002 /* Interrupt Enable */ | ||
240 | #define SPARC_PSTATE_AG 0x001 /* Alternate Globals */ | ||
241 | |||
242 | |||
243 | /* Condition Code Register bit definitions: */ | ||
244 | #define SPARC_CCR_XCC_MASK 0xf0 | ||
245 | #define SPARC_CCR_XCC_SHIFT 4 | ||
246 | #define SPARC_CCR_ICC_MASK 0x0f | ||
247 | #define SPARC_CCR_N 8 | ||
248 | #define SPARC_CCR_Z 4 | ||
249 | #define SPARC_CCR_V 2 | ||
250 | #define SPARC_CCR_C 1 | ||
251 | |||
252 | |||
253 | /* CWP, CANSAVE, CANRESTORE, OTHERWIN, CLEANWIN bitmask: */ | ||
254 | #define SPARC_CWP_MASK 0x1f | ||
255 | |||
256 | |||
257 | /* Window State bit definitions: */ | ||
258 | #define SPARC_WSTATE_OTHER_MASK 0x38 | ||
259 | #define SPARC_WSTATE_OTHER_SHIFT 3 | ||
260 | #define SPARC_WSTATE_NORMAL_MASK 0x07 | ||
261 | |||
262 | |||
263 | /* Tick Register bit definitions: */ | ||
264 | #define SPARC_TICK_NPT (1ULL << 63) /* Non-privileged trap */ | ||
265 | |||
266 | |||
267 | /* Addess Space Identifier bit definitions: */ | ||
268 | #define SPARC_ASI_RESTRICTED 0x80 | ||
269 | |||
270 | |||
271 | /* Trap Level Register bit definitions: */ | ||
272 | #define SPARC_TL_MASK 0x07 | ||
273 | |||
274 | |||
275 | /* Processor Interrupt Level Register bit definitions: */ | ||
276 | #define SPARC_PIL_MASK 0x0f | ||
277 | |||
278 | |||
279 | /* Trap Type Register bit definitions: */ | ||
280 | #define SPARC_TTYPE_MASK 0x1ff | ||
281 | |||
282 | |||
283 | /* Trap Base Address bit definitions: */ | ||
284 | #define SPARC_TBA_MASK 0xffffffffffff8000ULL | ||
285 | |||
286 | |||
287 | /* | ||
288 | * Full address for a trap is: | ||
289 | * TBA<bits 63..15> || X || TTYPE[TL] || 00000 | ||
290 | * | ||
291 | * where X is a bit which is true if TL>0 when the trap was taken. | ||
292 | */ | ||
293 | |||
294 | |||
295 | /* Version Register bit definitions: */ | ||
296 | #define SPARC_VER_MANUF_SHIFT 48 | ||
297 | #define SPARC_VER_IMPL_SHIFT 32 | ||
298 | #define SPARC_VER_MASK_SHIFT 24 | ||
299 | #define SPARC_VER_MAXTL_SHIFT 8 | ||
300 | #define SPARC_VER_MAXWIN_SHIFT 0 | ||
301 | |||
302 | |||
303 | dpavlin | 12 | /* cpu_sparc.c: */ |
304 | dpavlin | 24 | int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
305 | dpavlin | 12 | void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
306 | unsigned char *host_page, int writeflag, uint64_t paddr_page); | ||
307 | dpavlin | 18 | void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
308 | dpavlin | 14 | void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
309 | dpavlin | 22 | void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
310 | unsigned char *host_page, int writeflag, uint64_t paddr_page); | ||
311 | void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); | ||
312 | void sparc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); | ||
313 | dpavlin | 24 | void sparc_init_64bit_dummy_tables(struct cpu *cpu); |
314 | dpavlin | 12 | int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
315 | unsigned char *data, size_t len, int writeflag, int cache_flags); | ||
316 | int sparc_cpu_family_init(struct cpu_family *); | ||
317 | |||
318 | |||
319 | #endif /* CPU_SPARC_H */ |
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