/[gxemul]/trunk/src/include/cpu_sparc.h
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Annotation of /trunk/src/include/cpu_sparc.h

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Revision 18 - (hide annotations)
Mon Oct 8 16:19:11 2007 UTC (13 years, 3 months ago) by dpavlin
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File size: 4126 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1004 2005/10/27 14:01:10 debug Exp $
20051011        Passing -A as the default boot arg for CATS (works fine with
                OpenBSD/cats).
20051012	Fixing the VGA cursor offset bug, and speeding up framebuffer
		redraws if character cells contain the same thing as during
		the last redraw.
20051013	Adding a slow strd ARM instruction hack.
20051017	Minor updates: Adding a dummy i80321 Verde controller (for
		XScale emulation), fixing the disassembly of the ARM "ldrd"
		instruction, adding "support" for less-than-4KB pages for ARM
		(by not adding them to translation tables).
20051020	Continuing on some HPCarm stuff. A NetBSD/hpcarm kernel prints
		some boot messages on an emulated Jornada 720.
		Making dev_ram work better with dyntrans (speeds up some things
		quite a bit).
20051021	Automatically generating some of the most common ARM load/store
		multiple instructions.
20051022	Better statistics gathering for the ARM load/store multiple.
		Various other dyntrans and device updates.
20051023	Various minor updates.
20051024	Continuing; minor device and dyntrans fine-tuning. Adding the
		first "reasonable" instruction combination hacks for ARM (the
		cores of NetBSD/cats' memset and memcpy).
20051025	Fixing a dyntrans-related bug in dev_vga. Also changing the
		dyntrans low/high access notification to only be updated on
		writes, not reads. Hopefully it will be enough. (dev_vga in
		charcell mode now seems to work correctly with both reads and
		writes.)
		Experimenting with gathering dyntrans statistics (which parts
		of emulated RAM that are actually executed), and adding
		instruction combination hacks for cache cleaning and a part of
		NetBSD's scanc() function.
20051026	Adding a bitmap for ARM emulation which indicates if a page is
		(specifically) user accessible; loads and stores with the t-
		flag set can now use the translation arrays, which results in
		a measurable speedup.
20051027	Dyntrans updates; adding an extra bitmap array for 32-bit
		emulation modes, speeding up the check whether a physical page
		has any code translations or not (O(n) -> O(1)). Doing a
		similar reduction of O(n) to O(1) by avoiding the scan through
		the translation entries on a translation update (32-bit mode
		only).
		Various other minor hacks.
20051029	Quick release, without any testing at all.

==============  RELEASE 0.3.6.2  ==============


1 dpavlin 12 #ifndef CPU_SPARC_H
2     #define CPU_SPARC_H
3    
4     /*
5     * Copyright (C) 2005 Anders Gavare. All rights reserved.
6     *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 18 * $Id: cpu_sparc.h,v 1.12 2005/10/27 14:01:15 debug Exp $
32 dpavlin 12 */
33    
34     #include "misc.h"
35    
36    
37     struct cpu_family;
38    
39    
40     #define SPARC_N_IC_ARGS 3
41     #define SPARC_INSTR_ALIGNMENT_SHIFT 2
42     #define SPARC_IC_ENTRIES_SHIFT 10
43     #define SPARC_IC_ENTRIES_PER_PAGE (1 << SPARC_IC_ENTRIES_SHIFT)
44     #define SPARC_PC_TO_IC_ENTRY(a) (((a)>>SPARC_INSTR_ALIGNMENT_SHIFT) \
45     & (SPARC_IC_ENTRIES_PER_PAGE-1))
46     #define SPARC_ADDR_TO_PAGENR(a) ((a) >> (SPARC_IC_ENTRIES_SHIFT \
47     + SPARC_INSTR_ALIGNMENT_SHIFT))
48    
49     struct sparc_instr_call {
50     void (*f)(struct cpu *, struct sparc_instr_call *);
51     size_t arg[SPARC_N_IC_ARGS];
52     };
53    
54     /* Translation cache struct for each physical page: */
55     struct sparc_tc_physpage {
56 dpavlin 18 struct sparc_instr_call ics[SPARC_IC_ENTRIES_PER_PAGE + 1];
57 dpavlin 12 uint32_t next_ofs; /* or 0 for end of chain */
58 dpavlin 18 int flags;
59 dpavlin 12 uint64_t physaddr;
60     };
61    
62     #define SPARC_N_VPH_ENTRIES 1048576
63    
64     #define SPARC_MAX_VPH_TLB_ENTRIES 256
65     struct sparc_vpg_tlb_entry {
66     int valid;
67     int writeflag;
68     int64_t timestamp;
69     unsigned char *host_page;
70     uint64_t vaddr_page;
71     uint64_t paddr_page;
72     };
73    
74     struct sparc_cpu {
75     /* TODO */
76     uint64_t r_i[8];
77    
78    
79     /*
80     * Instruction translation cache:
81     */
82    
83     /* cur_ic_page is a pointer to an array of SPARC_IC_ENTRIES_PER_PAGE
84     instruction call entries. next_ic points to the next such
85     call to be executed. */
86     struct sparc_tc_physpage *cur_physpage;
87     struct sparc_instr_call *cur_ic_page;
88     struct sparc_instr_call *next_ic;
89    
90    
91     /*
92     * Virtual -> physical -> host address translation:
93     *
94     * host_load and host_store point to arrays of SPARC_N_VPH_ENTRIES
95     * pointers (to host pages); phys_addr points to an array of
96     * SPARC_N_VPH_ENTRIES uint32_t.
97     */
98    
99     struct sparc_vpg_tlb_entry vph_tlb_entry[SPARC_MAX_VPH_TLB_ENTRIES];
100     unsigned char *host_load[SPARC_N_VPH_ENTRIES];
101     unsigned char *host_store[SPARC_N_VPH_ENTRIES];
102     uint32_t phys_addr[SPARC_N_VPH_ENTRIES];
103     struct sparc_tc_physpage *phys_page[SPARC_N_VPH_ENTRIES];
104 dpavlin 18
105     uint32_t phystranslation[SPARC_N_VPH_ENTRIES/32];
106 dpavlin 12 };
107    
108    
109     /* cpu_sparc.c: */
110     void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
111     unsigned char *host_page, int writeflag, uint64_t paddr_page);
112 dpavlin 18 void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
113 dpavlin 14 void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
114 dpavlin 12 int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
115     unsigned char *data, size_t len, int writeflag, int cache_flags);
116     int sparc_cpu_family_init(struct cpu_family *);
117    
118    
119     #endif /* CPU_SPARC_H */

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