/[gxemul]/trunk/src/include/cpu_sh.h
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Contents of /trunk/src/include/cpu_sh.h

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Revision 36 - (show annotations)
Mon Oct 8 16:21:34 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 8916 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1497 2007/03/18 03:41:36 debug Exp $
20070224	Minor update to the initialization of the ns16550 in
		machine_walnut.c, to allow that machine type to boot with the
		new interrupt system (although it is still a dummy machine).
		Adding a wdc at 0x14000000 to machine_landisk.c, and fixing
		the SCIF serial interrupts of the SH4 cpu enough to get
		NetBSD/landisk booting from a disk image :-)  Adding a
		preliminary install instruction skeleton to guestoses.html.
20070306	Adding SH-IPL+G PROM emulation, and also passing the "end"
		symbol in r5 on bootup, for Landisk emulation. This is enough
		to get OpenBSD/landisk to install :)  Adding a preliminary
		install instruction skeleton to the documentation. SuperH
		emulation is still shaky, though :-/
20070307	Fixed a strangeness in memory_sh.c (read/write was never
		returned for any page). (Unknown whether this fixes any actual
		problems, though.)
20070308	dev_ram.c fix: invalidate code translations on writes to
		RAM, emulated as separate devices. Linux/dreamcast gets
		further in the boot process than before, but still bugs out
		in userland.
		Fixing bugs in the "stc.l gbr,@-rN" and "ldc.l @rN+,gbr" SuperH 
		instructions (they should NOT check the MD bit), allowing the
		Linux/dreamcast Live CD to reach userland correctly :-)
20070310	Changing the cpu name "Alpha" in src/useremul.c to "21364" to
		unbreak userland syscall emulation of FreeBSD/Alpha binaries.
20070314	Applying a patch from Michael Yaroslavtsev which fixes the
		previous Linux lib64 patch to the configure script.
20070315	Adding a (dummy) sun4v machine type, and SPARC T1 cpu type.
20070316	Creating a new directory, src/disk, and moving diskimage.c
		to it. Separating out bootblock loading stuff from emul.c into
		new files in src/disk.
		Adding some more SPARC registers.
20070318	Preparing/testing for a minirelease, 0.4.4.1.

==============  RELEASE 0.4.4.1  ==============


1 #ifndef CPU_SH_H
2 #define CPU_SH_H
3
4 /*
5 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_sh.h,v 1.38 2007/02/24 19:21:44 debug Exp $
32 *
33 * Note: Many things here are SH4-specific, so it probably doesn't work
34 * for SH3 emulation.
35 */
36
37 #include "interrupt.h"
38 #include "misc.h"
39 #include "sh4_cpu.h"
40
41
42 struct cpu_family;
43
44 /* SH CPU types: */
45 struct sh_cpu_type_def {
46 char *name;
47 int bits;
48 int arch;
49 uint32_t pvr;
50 uint32_t prr;
51 };
52
53 #define SH_CPU_TYPE_DEFS { \
54 { "SH7750", 32, 4, SH4_PVR_SH7750, 0 }, \
55 { "SH7750R", 32, 4, SH4_PVR_SH7750, SH4_PRR_7750R }, \
56 { "SH7751R", 32, 4, SH4_PVR_SH7751, SH4_PRR_7751R }, \
57 { "SH5", 64, 5, 0, 0 }, \
58 { NULL, 0, 0, 0, 0 } }
59
60
61 /*
62 * TODO: Figure out how to nicely support multiple instruction encodings!
63 * For now, I'm reverting this to SH4. SH5 will have to wait until later.
64 */
65
66 #define SH_N_IC_ARGS 2 /* 3 for SH5/SH64 */
67 #define SH_INSTR_ALIGNMENT_SHIFT 1 /* 2 for SH5/SH64 */
68 #define SH_IC_ENTRIES_SHIFT 11 /* 10 for SH5/SH64 */
69 #define SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT)
70 #define SH_PC_TO_IC_ENTRY(a) (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
71 & (SH_IC_ENTRIES_PER_PAGE-1))
72 #define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \
73 + SH_INSTR_ALIGNMENT_SHIFT))
74
75 DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_t)
76
77 #define SH_MAX_VPH_TLB_ENTRIES 128
78
79
80 #define SH_N_GPRS 16
81 #define SH_N_GPRS_BANKED 8
82 #define SH_N_FPRS 16
83
84 #define SH_N_ITLB_ENTRIES 4
85 #define SH_N_UTLB_ENTRIES 64
86
87 #define SH_INVALID_INSTR 0x00fb
88
89
90 struct sh_cpu {
91 struct sh_cpu_type_def cpu_type;
92
93 /* compact = 1 if currently executing 16-bit long opcodes */
94 int compact;
95
96 /* General Purpose Registers: */
97 uint32_t r[SH_N_GPRS];
98 uint32_t r_bank[SH_N_GPRS_BANKED];
99
100 /* Floating-Point Registers: */
101 uint32_t fr[SH_N_FPRS];
102 uint32_t xf[SH_N_FPRS]; /* "Other bank." */
103
104 uint32_t mach; /* Multiply-Accumulate High */
105 uint32_t macl; /* Multiply-Accumulate Low */
106 uint32_t pr; /* Procedure Register */
107 uint32_t fpscr; /* Floating-point Status/Control */
108 uint32_t fpul; /* Floating-point Communication Reg */
109 uint32_t sr; /* Status Register */
110 uint32_t ssr; /* Saved Status Register */
111 uint32_t spc; /* Saved PC */
112 uint32_t gbr; /* Global Base Register */
113 uint32_t vbr; /* Vector Base Register */
114 uint32_t sgr; /* Saved General Register */
115 uint32_t dbr; /* Debug Base Register */
116
117 /* Cache control: */
118 uint32_t ccr; /* Cache Control Register */
119 uint32_t qacr0; /* Queue Address Control Register 0 */
120 uint32_t qacr1; /* Queue Address Control Register 1 */
121
122 /* MMU/TLB registers: */
123 uint32_t pteh; /* Page Table Entry High */
124 uint32_t ptel; /* Page Table Entry Low */
125 uint32_t ptea; /* Page Table Entry A */
126 uint32_t ttb; /* Translation Table Base */
127 uint32_t tea; /* TLB Exception Address Register */
128 uint32_t mmucr; /* MMU Control Register */
129 uint32_t itlb_hi[SH_N_ITLB_ENTRIES];
130 uint32_t itlb_lo[SH_N_ITLB_ENTRIES];
131 uint32_t utlb_hi[SH_N_UTLB_ENTRIES];
132 uint32_t utlb_lo[SH_N_UTLB_ENTRIES];
133
134 /* Exception handling: */
135 uint32_t tra; /* TRAPA Exception Register */
136 uint32_t expevt; /* Exception Event Register */
137 uint32_t intevt; /* Interrupt Event Register */
138
139 /* Interrupt controller: */
140 uint16_t intc_ipra; /* Interrupt Priority Registers */
141 uint16_t intc_iprb;
142 uint16_t intc_iprc;
143 uint16_t intc_iprd;
144 int16_t int_to_assert; /* Calculated int to assert */
145 int int_level; /* Calculated int level */
146 uint32_t int_pending[0x1000 / 0x20 / (sizeof(uint32_t)*8)];
147
148 /* Timer/clock functionality: */
149 int pclock;
150
151 /* DMA Controller: (4 channels) */
152 uint32_t dmac_sar[4];
153 uint32_t dmac_dar[4];
154 uint32_t dmac_tcr[4];
155 uint32_t dmac_chcr[4];
156
157
158 /*
159 * Instruction translation cache and Virtual->Physical->Host
160 * address translation:
161 */
162 DYNTRANS_ITC(sh)
163 VPH_TLBS(sh,SH)
164 VPH32(sh,SH,uint64_t,uint8_t)
165 };
166
167
168 /* Status register bits: */
169 #define SH_SR_T 0x00000001 /* True/false */
170 #define SH_SR_S 0x00000002 /* Saturation */
171 #define SH_SR_IMASK 0x000000f0 /* Interrupt mask */
172 #define SH_SR_IMASK_SHIFT 4
173 #define SH_SR_Q 0x00000100 /* State for Divide Step */
174 #define SH_SR_M 0x00000200 /* State for Divide Step */
175 #define SH_SR_FD 0x00008000 /* FPU Disable */
176 #define SH_SR_BL 0x10000000 /* Exception/Interrupt Block */
177 #define SH_SR_RB 0x20000000 /* Register Bank 0/1 */
178 #define SH_SR_MD 0x40000000 /* Privileged Mode */
179
180 /* Floating-point status/control register bits: */
181 #define SH_FPSCR_RM_MASK 0x00000003 /* Rounding Mode */
182 #define SH_FPSCR_RM_NEAREST 0x0 /* Round to nearest */
183 #define SH_FPSCR_RM_ZERO 0x1 /* Round to zero */
184 #define SH_FPSCR_INEXACT 0x00000004 /* Inexact exception */
185 #define SH_FPSCR_UNDERFLOW 0x00000008 /* Underflow exception */
186 #define SH_FPSCR_OVERFLOW 0x00000010 /* Overflow exception */
187 #define SH_FPSCR_DIV_BY_ZERO 0x00000020 /* Div by zero exception */
188 #define SH_FPSCR_INVALID 0x00000040 /* Invalid exception */
189 #define SH_FPSCR_EN_INEXACT 0x00000080 /* Inexact enable */
190 #define SH_FPSCR_EN_UNDERFLOW 0x00000100 /* Underflow enable */
191 #define SH_FPSCR_EN_OVERFLOW 0x00000200 /* Overflow enable */
192 #define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400 /* Div by zero enable */
193 #define SH_FPSCR_EN_INVALID 0x00000800 /* Invalid enable */
194 #define SH_FPSCR_CAUSE_INEXACT 0x00001000 /* Cause Inexact */
195 #define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000 /* Cause Underflow */
196 #define SH_FPSCR_CAUSE_OVERFLOW 0x00004000 /* Cause Overflow */
197 #define SH_FPSCR_CAUSE_DIVBY0 0x00008000 /* Cause Div by 0 */
198 #define SH_FPSCR_CAUSE_INVALID 0x00010000 /* Cause Invalid */
199 #define SH_FPSCR_CAUSE_ERROR 0x00020000 /* Cause Error */
200 #define SH_FPSCR_DN_ZERO 0x00040000 /* Denormalization Mode */
201 #define SH_FPSCR_PR 0x00080000 /* Double-Precision Mode */
202 #define SH_FPSCR_SZ 0x00100000 /* Double-Precision Size */
203 #define SH_FPSCR_FR 0x00200000 /* Register Bank Select */
204
205
206 /* cpu_sh.c: */
207 void sh_cpu_interrupt_assert(struct interrupt *interrupt);
208 void sh_cpu_interrupt_deassert(struct interrupt *interrupt);
209 int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
210 int sh_run_instr(struct cpu *cpu);
211 void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
212 unsigned char *host_page, int writeflag, uint64_t paddr_page);
213 void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
214 void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
215 int sh32_run_instr(struct cpu *cpu);
216 void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
217 unsigned char *host_page, int writeflag, uint64_t paddr_page);
218 void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
219 void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
220 void sh_init_64bit_dummy_tables(struct cpu *cpu);
221 int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
222 unsigned char *data, size_t len, int writeflag, int cache_flags);
223 int sh_cpu_family_init(struct cpu_family *);
224
225 void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
226 void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr);
227
228 /* memory_sh.c: */
229 int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
230 uint64_t *return_addr, int flags);
231
232
233 #endif /* CPU_SH_H */

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