/[gxemul]/trunk/src/include/cpu_sh.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 28 by dpavlin, Mon Oct 8 16:20:26 2007 UTC revision 30 by dpavlin, Mon Oct 8 16:20:40 2007 UTC
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_sh.h,v 1.17 2006/07/16 13:32:28 debug Exp $   *  $Id: cpu_sh.h,v 1.21 2006/07/25 21:49:14 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 36  Line 36 
36    
37  struct cpu_family;  struct cpu_family;
38    
39    /*  SH CPU types:  */
40    struct sh_cpu_type_def {
41            char            *name;
42            int             bits;
43    };
44    
45    #define SH_CPU_TYPE_DEFS        {       \
46            { "SH3", 32 },                  \
47            { "SH4", 32 },                  \
48            { "SH5", 64 },                  \
49            { NULL, 0 } }
50    
51    
52  #define SH_N_IC_ARGS                    3  /*
53  #define SH_INSTR_ALIGNMENT_SHIFT        2   *  TODO: Figure out how to nicely support multiple instruction encodings!
54  #define SH_IC_ENTRIES_SHIFT             10   *  For now, I'm reverting this to SH4. SH5 will have to wait until later.
55     */
56    
57    #define SH_N_IC_ARGS                    2       /*  3 for SH5/SH64  */
58    #define SH_INSTR_ALIGNMENT_SHIFT        1       /*  2 for SH5/SH64  */
59    #define SH_IC_ENTRIES_SHIFT             11      /*  10 for SH5/SH64  */
60  #define SH_IC_ENTRIES_PER_PAGE          (1 << SH_IC_ENTRIES_SHIFT)  #define SH_IC_ENTRIES_PER_PAGE          (1 << SH_IC_ENTRIES_SHIFT)
61  #define SH_PC_TO_IC_ENTRY(a)            (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \  #define SH_PC_TO_IC_ENTRY(a)            (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
62                                          & (SH_IC_ENTRIES_PER_PAGE-1))                                          & (SH_IC_ENTRIES_PER_PAGE-1))
# Line 55  DYNTRANS_MISC64_DECLARATIONS(sh,SH,uint8 Line 72  DYNTRANS_MISC64_DECLARATIONS(sh,SH,uint8
72  #define SH_MAX_VPH_TLB_ENTRIES          128  #define SH_MAX_VPH_TLB_ENTRIES          128
73    
74    
75    #define SH_N_GPRS               64
76    
77    
78  struct sh_cpu {  struct sh_cpu {
79          int             bits;          struct sh_cpu_type_def cpu_type;
80    
81            /*  compact = 1 if currently executing 16-bit long opcodes  */
82          int             compact;          int             compact;
83    
84          uint64_t        r[64];          uint32_t        r_otherbank[8];
85    
86            uint64_t        r[SH_N_GPRS];
87    
88            uint32_t        mach;           /*  Multiply-Accumulate High  */
89            uint32_t        macl;           /*  Multiply-Accumulate Low  */
90            uint32_t        pr;             /*  Procedure Register  */
91            uint32_t        fpscr;          /*  Floating-point Status/Control  */
92            uint32_t        fpul;           /*  Floating-point Communication Reg  */
93            uint32_t        sr;             /*  Status Register  */
94            uint32_t        ssr;            /*  Saved Status Register  */
95            uint32_t        spc;            /*  Saved PC  */
96            uint32_t        gbr;            /*  Global Base Register  */
97            uint32_t        vbr;            /*  Vector Base Register  */
98            uint32_t        sgr;            /*  Saved General Register  */
99            uint32_t        dbr;            /*  Debug Base Register  */
100    
101    
102          /*          /*
# Line 73  struct sh_cpu { Line 110  struct sh_cpu {
110  };  };
111    
112    
113    /*  Status register bits:  */
114    #define SH_SR_T                 0x00000001      /*  True/false  */
115    #define SH_SR_S                 0x00000002      /*  Saturation  */
116    #define SH_SR_IMASK             0x000000f0      /*  Interrupt mask  */
117    #define SH_SR_IMASK_SHIFT               4
118    #define SH_SR_Q                 0x00000100      /*  State for Divide Step  */
119    #define SH_SR_M                 0x00000200      /*  State for Divide Step  */
120    #define SH_SR_FD                0x00008000      /*  FPU Disable  */
121    #define SH_SR_BL                0x10000000      /*  Exception/Interrupt Block */
122    #define SH_SR_RB                0x20000000      /*  Register Bank 0/1  */
123    #define SH_SR_MD                0x40000000      /*  Privileged Mode  */
124    
125    
126  /*  cpu_sh.c:  */  /*  cpu_sh.c:  */
127  int sh_run_instr(struct cpu *cpu);  int sh_run_instr(struct cpu *cpu);
128  void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
# Line 89  int sh_memory_rw(struct cpu *cpu, struct Line 139  int sh_memory_rw(struct cpu *cpu, struct
139          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
140  int sh_cpu_family_init(struct cpu_family *);  int sh_cpu_family_init(struct cpu_family *);
141    
142    void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
143    
144    /*  memory_sh.c:  */
145    int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
146            uint64_t *return_addr, int flags);
147    
148    
149  #endif  /*  CPU_SH_H  */  #endif  /*  CPU_SH_H  */
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