/[gxemul]/trunk/src/include/cpu_sh.h
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Contents of /trunk/src/include/cpu_sh.h

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Revision 44 - (show annotations)
Mon Oct 8 16:22:56 2007 UTC (11 years, 10 months ago) by dpavlin
File MIME type: text/plain
File size: 9092 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1632 2007/09/11 21:46:35 debug Exp $
20070616	Implementing the MIPS32/64 revision 2 "ror" instruction.
20070617	Adding a struct for each physpage which keeps track of which
		ranges within that page (base offset, length) that are
		continuously translatable. When running with native code
		generation enabled (-b), a range is added after each read-
		ahead loop.
		Experimenting with using the physical program counter sample
		data (implemented 20070608) together with the "translatable
		range" information, to figure out which physical address ranges
		would be worth translating to native code (if the number of
		samples falling within a range is above a certain threshold).
20070618	Adding automagic building of .index comment files for
		src/file/, src/promemul/, src src/useremul/ as well.
		Adding a "has been translated" bit to the ranges, so that only
		not-yet-translated ranges will be sampled.
20070619	Moving src/cpu.c and src/memory_rw.c into src/cpus/,
		src/device.c into src/devices/, and src/machine.c into
		src/machines/.
		Creating a skeleton cc/ld native backend module; beginning on
		the function which will detect cc command line, etc.
20070620	Continuing on the native code generation infrastructure.
20070621	Moving src/x11.c and src/console.c into a new src/console/
		subdir (for everything that is console or framebuffer related).
		Moving src/symbol*.c into a new src/symbol/, which should
		contain anything that is symbol handling related.
20070624	Making the program counter sampling threshold a "settings
		variable" (sampling_threshold), i.e. it can now be changed
		during runtime.
		Switching the RELEASE notes format from plain text to HTML.
		If the TMPDIR environment variable is set, it is used instead
		of "/tmp" for temporary files.
		Continuing on the cc/ld backend: simple .c code is generated,
		the compiler and linker are called, etc.
		Adding detection of host architecture to the configure script
		(again), and adding icache invalidation support (only
		implemented for Alpha hosts so far).
20070625	Simplifying the program counter sampling mechanism.
20070626	Removing the cc/ld native code generation stuff, program
		counter sampling, etc; it would not have worked well in the
		general case.
20070627	Removing everything related to native code generation.
20070629	Removing the (practically unusable) support for multiple
		emulations. (The single emulation allowed now still supports
		multiple simultaneous machines, as before.)
		Beginning on PCCTWO and M88K interrupts.
20070723	Adding a dummy skeleton for emulation of M32R processors.
20070901	Fixing a warning found by "gcc version 4.3.0 20070817
		(experimental)" on amd64.
20070905	Removing some more traces of the old "multiple emulations"
		code.
		Also looking in /usr/local/include and /usr/local/lib for
		X11 libs, when running configure.
20070909	Minor updates to the guest OS install instructions, in
		preparation for the NetBSD 4.0 release.
20070918	More testing of NetBSD 4.0 RC1.

1 #ifndef CPU_SH_H
2 #define CPU_SH_H
3
4 /*
5 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_sh.h,v 1.50 2007/07/20 09:03:33 debug Exp $
32 *
33 * Note 1: Many things here are SH4-specific, so it probably doesn't work
34 * for SH3 emulation.
35 *
36 * Note 2: The SuperH emulation in GXemul does not include SH5/SH64 at
37 * this time. There doesn't seem to be that much interesting code
38 * to run in the emulator for SH5. :-/
39 */
40
41 #include "interrupt.h"
42 #include "misc.h"
43 #include "sh4_cpu.h"
44
45
46 struct cpu_family;
47
48
49 /* SH CPU types: */
50 struct sh_cpu_type_def {
51 char *name;
52 int bits;
53 int arch;
54 uint32_t pvr;
55 uint32_t prr;
56 };
57
58 #define SH_CPU_TYPE_DEFS { \
59 { "SH7708R", 32, 3, 0, 0, }, \
60 { "SH7750", 32, 4, SH4_PVR_SH7750, 0 }, \
61 { "SH7750R", 32, 4, SH4_PVR_SH7750, SH4_PRR_7750R }, \
62 { "SH7751R", 32, 4, SH4_PVR_SH7751, SH4_PRR_7751R }, \
63 /* { "SH5", 64, 5, 0, 0 }, */ \
64 { NULL, 0, 0, 0, 0 } }
65
66
67 #define SH_N_IC_ARGS 2
68 #define SH_INSTR_ALIGNMENT_SHIFT 1
69 #define SH_IC_ENTRIES_SHIFT 11
70 #define SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT)
71 #define SH_PC_TO_IC_ENTRY(a) (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
72 & (SH_IC_ENTRIES_PER_PAGE-1))
73 #define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \
74 + SH_INSTR_ALIGNMENT_SHIFT))
75
76 DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_t)
77
78 #define SH_MAX_VPH_TLB_ENTRIES 128
79
80
81 #define SH_N_GPRS 16
82 #define SH_N_GPRS_BANKED 8
83 #define SH_N_FPRS 16
84
85 #define SH_N_ITLB_ENTRIES 4
86 #define SH_N_UTLB_ENTRIES 64
87
88 /* An instruction with an invalid encoding; used for software
89 emulation of PROM calls within GXemul: */
90 #define SH_INVALID_INSTR 0x00fb
91
92
93 struct sh_cpu {
94 struct sh_cpu_type_def cpu_type;
95
96 /* General Purpose Registers: */
97 uint32_t r[SH_N_GPRS];
98 uint32_t r_bank[SH_N_GPRS_BANKED];
99
100 /* Floating-Point Registers: */
101 uint32_t fr[SH_N_FPRS];
102 uint32_t xf[SH_N_FPRS]; /* "Other bank." */
103
104 uint32_t mach; /* Multiply-Accumulate High */
105 uint32_t macl; /* Multiply-Accumulate Low */
106 uint32_t pr; /* Procedure Register */
107 uint32_t fpscr; /* Floating-point Status/Control */
108 uint32_t fpul; /* Floating-point Communication Reg */
109 uint32_t sr; /* Status Register */
110 uint32_t ssr; /* Saved Status Register */
111 uint32_t spc; /* Saved PC */
112 uint32_t gbr; /* Global Base Register */
113 uint32_t vbr; /* Vector Base Register */
114 uint32_t sgr; /* Saved General Register */
115 uint32_t dbr; /* Debug Base Register */
116
117 /* Cache control: */
118 uint32_t ccr; /* Cache Control Register */
119 uint32_t qacr0; /* Queue Address Control Register 0 */
120 uint32_t qacr1; /* Queue Address Control Register 1 */
121
122 /* MMU/TLB registers: */
123 uint32_t pteh; /* Page Table Entry High */
124 uint32_t ptel; /* Page Table Entry Low */
125 uint32_t ptea; /* Page Table Entry A */
126 uint32_t ttb; /* Translation Table Base */
127 uint32_t tea; /* TLB Exception Address Register */
128 uint32_t mmucr; /* MMU Control Register */
129 uint32_t itlb_hi[SH_N_ITLB_ENTRIES];
130 uint32_t itlb_lo[SH_N_ITLB_ENTRIES];
131 uint32_t utlb_hi[SH_N_UTLB_ENTRIES];
132 uint32_t utlb_lo[SH_N_UTLB_ENTRIES];
133
134 /* Exception handling: */
135 uint32_t tra; /* TRAPA Exception Register */
136 uint32_t expevt; /* Exception Event Register */
137 uint32_t intevt; /* Interrupt Event Register */
138
139 /* Interrupt controller: */
140 uint16_t intc_ipra; /* Interrupt Priority Registers */
141 uint16_t intc_iprb;
142 uint16_t intc_iprc;
143 uint16_t intc_iprd;
144 uint32_t intc_intpri00;
145 uint32_t intc_intpri04;
146 uint32_t intc_intpri08;
147 uint32_t intc_intpri0c;
148 uint32_t intc_intreq00;
149 uint32_t intc_intreq04;
150 uint32_t intc_intmsk00;
151 uint32_t intc_intmsk04;
152 /* Cached and calculated values: */
153 uint8_t int_prio_and_pending[0x1000 / 0x20];
154 int16_t int_to_assert; /* Calculated int to assert */
155 unsigned int int_level; /* Calculated int level */
156
157 /* Timer/clock functionality: */
158 int pclock;
159
160 /* DMA Controller: (4 channels) */
161 uint32_t dmac_sar[4];
162 uint32_t dmac_dar[4];
163 uint32_t dmac_tcr[4];
164 uint32_t dmac_chcr[4];
165
166 /* PCI controller: */
167 struct pci_data *pcic_pcibus;
168
169
170 /*
171 * Instruction translation cache and Virtual->Physical->Host
172 * address translation:
173 */
174 DYNTRANS_ITC(sh)
175 VPH_TLBS(sh,SH)
176 VPH32(sh,SH)
177 };
178
179
180 /* Status register bits: */
181 #define SH_SR_T 0x00000001 /* True/false */
182 #define SH_SR_S 0x00000002 /* Saturation */
183 #define SH_SR_IMASK 0x000000f0 /* Interrupt mask */
184 #define SH_SR_IMASK_SHIFT 4
185 #define SH_SR_Q 0x00000100 /* State for Divide Step */
186 #define SH_SR_M 0x00000200 /* State for Divide Step */
187 #define SH_SR_FD 0x00008000 /* FPU Disable */
188 #define SH_SR_BL 0x10000000 /* Exception/Interrupt Block */
189 #define SH_SR_RB 0x20000000 /* Register Bank 0/1 */
190 #define SH_SR_MD 0x40000000 /* Privileged Mode */
191
192 /* Floating-point status/control register bits: */
193 #define SH_FPSCR_RM_MASK 0x00000003 /* Rounding Mode */
194 #define SH_FPSCR_RM_NEAREST 0x0 /* Round to nearest */
195 #define SH_FPSCR_RM_ZERO 0x1 /* Round to zero */
196 #define SH_FPSCR_INEXACT 0x00000004 /* Inexact exception */
197 #define SH_FPSCR_UNDERFLOW 0x00000008 /* Underflow exception */
198 #define SH_FPSCR_OVERFLOW 0x00000010 /* Overflow exception */
199 #define SH_FPSCR_DIV_BY_ZERO 0x00000020 /* Div by zero exception */
200 #define SH_FPSCR_INVALID 0x00000040 /* Invalid exception */
201 #define SH_FPSCR_EN_INEXACT 0x00000080 /* Inexact enable */
202 #define SH_FPSCR_EN_UNDERFLOW 0x00000100 /* Underflow enable */
203 #define SH_FPSCR_EN_OVERFLOW 0x00000200 /* Overflow enable */
204 #define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400 /* Div by zero enable */
205 #define SH_FPSCR_EN_INVALID 0x00000800 /* Invalid enable */
206 #define SH_FPSCR_CAUSE_INEXACT 0x00001000 /* Cause Inexact */
207 #define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000 /* Cause Underflow */
208 #define SH_FPSCR_CAUSE_OVERFLOW 0x00004000 /* Cause Overflow */
209 #define SH_FPSCR_CAUSE_DIVBY0 0x00008000 /* Cause Div by 0 */
210 #define SH_FPSCR_CAUSE_INVALID 0x00010000 /* Cause Invalid */
211 #define SH_FPSCR_CAUSE_ERROR 0x00020000 /* Cause Error */
212 #define SH_FPSCR_DN_ZERO 0x00040000 /* Denormalization Mode */
213 #define SH_FPSCR_PR 0x00080000 /* Double-Precision Mode */
214 #define SH_FPSCR_SZ 0x00100000 /* Double-Precision Size */
215 #define SH_FPSCR_FR 0x00200000 /* Register Bank Select */
216
217
218 /* int_prio_and_pending bits: */
219 #define SH_INT_ASSERTED 0x10
220 #define SH_INT_PRIO_MASK 0x0f
221
222 /* cpu_sh.c: */
223 void sh_cpu_interrupt_assert(struct interrupt *interrupt);
224 void sh_cpu_interrupt_deassert(struct interrupt *interrupt);
225 int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
226 int sh_run_instr(struct cpu *cpu);
227 void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
228 unsigned char *host_page, int writeflag, uint64_t paddr_page);
229 void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
230 void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
231 void sh_init_64bit_dummy_tables(struct cpu *cpu);
232 int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
233 unsigned char *data, size_t len, int writeflag, int cache_flags);
234 int sh_cpu_family_init(struct cpu_family *);
235
236 void sh_update_interrupt_priorities(struct cpu *cpu);
237 void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
238 void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr);
239
240 /* memory_sh.c: */
241 int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
242 uint64_t *return_addr, int flags);
243
244
245 #endif /* CPU_SH_H */

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