/[gxemul]/trunk/src/include/cpu_sh.h
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Contents of /trunk/src/include/cpu_sh.h

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Revision 42 - (show annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 9391 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============
1 #ifndef CPU_SH_H
2 #define CPU_SH_H
3
4 /*
5 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_sh.h,v 1.46 2007/06/07 15:36:25 debug Exp $
32 *
33 * Note: Many things here are SH4-specific, so it probably doesn't work
34 * for SH3 emulation.
35 */
36
37 #include "interrupt.h"
38 #include "misc.h"
39 #include "sh4_cpu.h"
40
41
42 struct cpu_family;
43 struct timer;
44
45
46 /* SH CPU types: */
47 struct sh_cpu_type_def {
48 char *name;
49 int bits;
50 int arch;
51 uint32_t pvr;
52 uint32_t prr;
53 };
54
55 #define SH_CPU_TYPE_DEFS { \
56 { "SH7708R", 32, 3, 0, 0, }, \
57 { "SH7750", 32, 4, SH4_PVR_SH7750, 0 }, \
58 { "SH7750R", 32, 4, SH4_PVR_SH7750, SH4_PRR_7750R }, \
59 { "SH7751R", 32, 4, SH4_PVR_SH7751, SH4_PRR_7751R }, \
60 /* { "SH5", 64, 5, 0, 0 }, */ \
61 { NULL, 0, 0, 0, 0 } }
62
63
64 /*
65 * TODO: Figure out how to nicely support multiple instruction encodings!
66 * For now, I'm reverting this to SH4. SH5 will have to wait until later.
67 */
68
69 #define SH_N_IC_ARGS 2 /* 3 for SH5/SH64 */
70 #define SH_INSTR_ALIGNMENT_SHIFT 1 /* 2 for SH5/SH64 */
71 #define SH_IC_ENTRIES_SHIFT 11 /* 10 for SH5/SH64 */
72 #define SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT)
73 #define SH_PC_TO_IC_ENTRY(a) (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
74 & (SH_IC_ENTRIES_PER_PAGE-1))
75 #define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \
76 + SH_INSTR_ALIGNMENT_SHIFT))
77
78 DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_t)
79
80 #define SH_MAX_VPH_TLB_ENTRIES 128
81
82
83 #define SH_N_GPRS 16
84 #define SH_N_GPRS_BANKED 8
85 #define SH_N_FPRS 16
86
87 #define SH_N_ITLB_ENTRIES 4
88 #define SH_N_UTLB_ENTRIES 64
89
90 #define SH_INVALID_INSTR 0x00fb
91
92
93 struct sh_cpu {
94 struct sh_cpu_type_def cpu_type;
95
96 /* General Purpose Registers: */
97 uint32_t r[SH_N_GPRS];
98 uint32_t r_bank[SH_N_GPRS_BANKED];
99
100 /* Floating-Point Registers: */
101 uint32_t fr[SH_N_FPRS];
102 uint32_t xf[SH_N_FPRS]; /* "Other bank." */
103
104 uint32_t mach; /* Multiply-Accumulate High */
105 uint32_t macl; /* Multiply-Accumulate Low */
106 uint32_t pr; /* Procedure Register */
107 uint32_t fpscr; /* Floating-point Status/Control */
108 uint32_t fpul; /* Floating-point Communication Reg */
109 uint32_t sr; /* Status Register */
110 uint32_t ssr; /* Saved Status Register */
111 uint32_t spc; /* Saved PC */
112 uint32_t gbr; /* Global Base Register */
113 uint32_t vbr; /* Vector Base Register */
114 uint32_t sgr; /* Saved General Register */
115 uint32_t dbr; /* Debug Base Register */
116
117 /* Cache control: */
118 uint32_t ccr; /* Cache Control Register */
119 uint32_t qacr0; /* Queue Address Control Register 0 */
120 uint32_t qacr1; /* Queue Address Control Register 1 */
121
122 /* MMU/TLB registers: */
123 uint32_t pteh; /* Page Table Entry High */
124 uint32_t ptel; /* Page Table Entry Low */
125 uint32_t ptea; /* Page Table Entry A */
126 uint32_t ttb; /* Translation Table Base */
127 uint32_t tea; /* TLB Exception Address Register */
128 uint32_t mmucr; /* MMU Control Register */
129 uint32_t itlb_hi[SH_N_ITLB_ENTRIES];
130 uint32_t itlb_lo[SH_N_ITLB_ENTRIES];
131 uint32_t utlb_hi[SH_N_UTLB_ENTRIES];
132 uint32_t utlb_lo[SH_N_UTLB_ENTRIES];
133
134 /* Exception handling: */
135 uint32_t tra; /* TRAPA Exception Register */
136 uint32_t expevt; /* Exception Event Register */
137 uint32_t intevt; /* Interrupt Event Register */
138
139 /* Interrupt controller: */
140 uint16_t intc_ipra; /* Interrupt Priority Registers */
141 uint16_t intc_iprb;
142 uint16_t intc_iprc;
143 uint16_t intc_iprd;
144 uint32_t intc_intpri00;
145 uint32_t intc_intpri04;
146 uint32_t intc_intpri08;
147 uint32_t intc_intpri0c;
148 uint32_t intc_intreq00;
149 uint32_t intc_intreq04;
150 uint32_t intc_intmsk00;
151 uint32_t intc_intmsk04;
152 /* Cached and calculated values: */
153 uint8_t int_prio_and_pending[0x1000 / 0x20];
154 int16_t int_to_assert; /* Calculated int to assert */
155 unsigned int int_level; /* Calculated int level */
156
157 /* Timer/clock functionality: */
158 int pclock;
159
160 /* DMA Controller: (4 channels) */
161 uint32_t dmac_sar[4];
162 uint32_t dmac_dar[4];
163 uint32_t dmac_tcr[4];
164 uint32_t dmac_chcr[4];
165
166 /* PCI controller: */
167 struct pci_data *pcic_pcibus;
168
169
170 /*
171 * Instruction translation cache and Virtual->Physical->Host
172 * address translation:
173 */
174 DYNTRANS_ITC(sh)
175 VPH_TLBS(sh,SH)
176 VPH32(sh,SH)
177 };
178
179
180 /* Status register bits: */
181 #define SH_SR_T 0x00000001 /* True/false */
182 #define SH_SR_S 0x00000002 /* Saturation */
183 #define SH_SR_IMASK 0x000000f0 /* Interrupt mask */
184 #define SH_SR_IMASK_SHIFT 4
185 #define SH_SR_Q 0x00000100 /* State for Divide Step */
186 #define SH_SR_M 0x00000200 /* State for Divide Step */
187 #define SH_SR_FD 0x00008000 /* FPU Disable */
188 #define SH_SR_BL 0x10000000 /* Exception/Interrupt Block */
189 #define SH_SR_RB 0x20000000 /* Register Bank 0/1 */
190 #define SH_SR_MD 0x40000000 /* Privileged Mode */
191
192 /* Floating-point status/control register bits: */
193 #define SH_FPSCR_RM_MASK 0x00000003 /* Rounding Mode */
194 #define SH_FPSCR_RM_NEAREST 0x0 /* Round to nearest */
195 #define SH_FPSCR_RM_ZERO 0x1 /* Round to zero */
196 #define SH_FPSCR_INEXACT 0x00000004 /* Inexact exception */
197 #define SH_FPSCR_UNDERFLOW 0x00000008 /* Underflow exception */
198 #define SH_FPSCR_OVERFLOW 0x00000010 /* Overflow exception */
199 #define SH_FPSCR_DIV_BY_ZERO 0x00000020 /* Div by zero exception */
200 #define SH_FPSCR_INVALID 0x00000040 /* Invalid exception */
201 #define SH_FPSCR_EN_INEXACT 0x00000080 /* Inexact enable */
202 #define SH_FPSCR_EN_UNDERFLOW 0x00000100 /* Underflow enable */
203 #define SH_FPSCR_EN_OVERFLOW 0x00000200 /* Overflow enable */
204 #define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400 /* Div by zero enable */
205 #define SH_FPSCR_EN_INVALID 0x00000800 /* Invalid enable */
206 #define SH_FPSCR_CAUSE_INEXACT 0x00001000 /* Cause Inexact */
207 #define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000 /* Cause Underflow */
208 #define SH_FPSCR_CAUSE_OVERFLOW 0x00004000 /* Cause Overflow */
209 #define SH_FPSCR_CAUSE_DIVBY0 0x00008000 /* Cause Div by 0 */
210 #define SH_FPSCR_CAUSE_INVALID 0x00010000 /* Cause Invalid */
211 #define SH_FPSCR_CAUSE_ERROR 0x00020000 /* Cause Error */
212 #define SH_FPSCR_DN_ZERO 0x00040000 /* Denormalization Mode */
213 #define SH_FPSCR_PR 0x00080000 /* Double-Precision Mode */
214 #define SH_FPSCR_SZ 0x00100000 /* Double-Precision Size */
215 #define SH_FPSCR_FR 0x00200000 /* Register Bank Select */
216
217
218 /* int_prio_and_pending bits: */
219 #define SH_INT_ASSERTED 0x10
220 #define SH_INT_PRIO_MASK 0x0f
221
222 /* cpu_sh.c: */
223 void sh_cpu_interrupt_assert(struct interrupt *interrupt);
224 void sh_cpu_interrupt_deassert(struct interrupt *interrupt);
225 int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
226 int sh_run_instr(struct cpu *cpu);
227 void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
228 unsigned char *host_page, int writeflag, uint64_t paddr_page);
229 void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
230 void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
231 int sh32_run_instr(struct cpu *cpu);
232 void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
233 unsigned char *host_page, int writeflag, uint64_t paddr_page);
234 void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
235 void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
236 void sh_init_64bit_dummy_tables(struct cpu *cpu);
237 void sh_timer_sample_tick(struct timer *, void *);
238 int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
239 unsigned char *data, size_t len, int writeflag, int cache_flags);
240 int sh_cpu_family_init(struct cpu_family *);
241
242 void sh_update_interrupt_priorities(struct cpu *cpu);
243 void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
244 void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr);
245
246 /* memory_sh.c: */
247 int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
248 uint64_t *return_addr, int flags);
249
250
251 #endif /* CPU_SH_H */
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