/[gxemul]/trunk/src/include/cpu_sh.h
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Contents of /trunk/src/include/cpu_sh.h

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 8749 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 #ifndef CPU_SH_H
2 #define CPU_SH_H
3
4 /*
5 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_sh.h,v 1.37 2006/12/30 13:31:00 debug Exp $
32 *
33 * Note: Many things here are SH4-specific, so it probably doesn't work
34 * for SH3 emulation.
35 */
36
37 #include "interrupt.h"
38 #include "misc.h"
39 #include "sh4_cpu.h"
40
41
42 struct cpu_family;
43
44 /* SH CPU types: */
45 struct sh_cpu_type_def {
46 char *name;
47 int bits;
48 int arch;
49 uint32_t pvr;
50 uint32_t prr;
51 };
52
53 #define SH_CPU_TYPE_DEFS { \
54 { "SH7750", 32, 4, SH4_PVR_SH7750, 0 }, \
55 { "SH5", 64, 5, 0, 0 }, \
56 { NULL, 0, 0, 0, 0 } }
57
58
59 /*
60 * TODO: Figure out how to nicely support multiple instruction encodings!
61 * For now, I'm reverting this to SH4. SH5 will have to wait until later.
62 */
63
64 #define SH_N_IC_ARGS 2 /* 3 for SH5/SH64 */
65 #define SH_INSTR_ALIGNMENT_SHIFT 1 /* 2 for SH5/SH64 */
66 #define SH_IC_ENTRIES_SHIFT 11 /* 10 for SH5/SH64 */
67 #define SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT)
68 #define SH_PC_TO_IC_ENTRY(a) (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
69 & (SH_IC_ENTRIES_PER_PAGE-1))
70 #define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \
71 + SH_INSTR_ALIGNMENT_SHIFT))
72
73 DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_t)
74
75 #define SH_MAX_VPH_TLB_ENTRIES 128
76
77
78 #define SH_N_GPRS 16
79 #define SH_N_GPRS_BANKED 8
80 #define SH_N_FPRS 16
81
82 #define SH_N_ITLB_ENTRIES 4
83 #define SH_N_UTLB_ENTRIES 64
84
85 #define SH_INVALID_INSTR 0x00fb
86
87
88 struct sh_cpu {
89 struct sh_cpu_type_def cpu_type;
90
91 /* compact = 1 if currently executing 16-bit long opcodes */
92 int compact;
93
94 /* General Purpose Registers: */
95 uint32_t r[SH_N_GPRS];
96 uint32_t r_bank[SH_N_GPRS_BANKED];
97
98 /* Floating-Point Registers: */
99 uint32_t fr[SH_N_FPRS];
100 uint32_t xf[SH_N_FPRS]; /* "Other bank." */
101
102 uint32_t mach; /* Multiply-Accumulate High */
103 uint32_t macl; /* Multiply-Accumulate Low */
104 uint32_t pr; /* Procedure Register */
105 uint32_t fpscr; /* Floating-point Status/Control */
106 uint32_t fpul; /* Floating-point Communication Reg */
107 uint32_t sr; /* Status Register */
108 uint32_t ssr; /* Saved Status Register */
109 uint32_t spc; /* Saved PC */
110 uint32_t gbr; /* Global Base Register */
111 uint32_t vbr; /* Vector Base Register */
112 uint32_t sgr; /* Saved General Register */
113 uint32_t dbr; /* Debug Base Register */
114
115 /* Cache control: */
116 uint32_t ccr; /* Cache Control Register */
117 uint32_t qacr0; /* Queue Address Control Register 0 */
118 uint32_t qacr1; /* Queue Address Control Register 1 */
119
120 /* MMU/TLB registers: */
121 uint32_t pteh; /* Page Table Entry High */
122 uint32_t ptel; /* Page Table Entry Low */
123 uint32_t ptea; /* Page Table Entry A */
124 uint32_t ttb; /* Translation Table Base */
125 uint32_t tea; /* TLB Exception Address Register */
126 uint32_t mmucr; /* MMU Control Register */
127 uint32_t itlb_hi[SH_N_ITLB_ENTRIES];
128 uint32_t itlb_lo[SH_N_ITLB_ENTRIES];
129 uint32_t utlb_hi[SH_N_UTLB_ENTRIES];
130 uint32_t utlb_lo[SH_N_UTLB_ENTRIES];
131
132 /* Exception handling: */
133 uint32_t tra; /* TRAPA Exception Register */
134 uint32_t expevt; /* Exception Event Register */
135 uint32_t intevt; /* Interrupt Event Register */
136
137 /* Interrupt controller: */
138 uint16_t intc_ipra; /* Interrupt Priority Registers */
139 uint16_t intc_iprb;
140 uint16_t intc_iprc;
141 uint16_t intc_iprd;
142 int16_t int_to_assert; /* Calculated int to assert */
143 int int_level; /* Calculated int level */
144 uint32_t int_pending[0x1000 / 0x20 / (sizeof(uint32_t)*8)];
145
146 /* Timer/clock functionality: */
147 int pclock;
148
149 /* DMA Controller: (4 channels) */
150 uint32_t dmac_sar[4];
151 uint32_t dmac_dar[4];
152 uint32_t dmac_tcr[4];
153 uint32_t dmac_chcr[4];
154
155
156 /*
157 * Instruction translation cache and Virtual->Physical->Host
158 * address translation:
159 */
160 DYNTRANS_ITC(sh)
161 VPH_TLBS(sh,SH)
162 VPH32(sh,SH,uint64_t,uint8_t)
163 };
164
165
166 /* Status register bits: */
167 #define SH_SR_T 0x00000001 /* True/false */
168 #define SH_SR_S 0x00000002 /* Saturation */
169 #define SH_SR_IMASK 0x000000f0 /* Interrupt mask */
170 #define SH_SR_IMASK_SHIFT 4
171 #define SH_SR_Q 0x00000100 /* State for Divide Step */
172 #define SH_SR_M 0x00000200 /* State for Divide Step */
173 #define SH_SR_FD 0x00008000 /* FPU Disable */
174 #define SH_SR_BL 0x10000000 /* Exception/Interrupt Block */
175 #define SH_SR_RB 0x20000000 /* Register Bank 0/1 */
176 #define SH_SR_MD 0x40000000 /* Privileged Mode */
177
178 /* Floating-point status/control register bits: */
179 #define SH_FPSCR_RM_MASK 0x00000003 /* Rounding Mode */
180 #define SH_FPSCR_RM_NEAREST 0x0 /* Round to nearest */
181 #define SH_FPSCR_RM_ZERO 0x1 /* Round to zero */
182 #define SH_FPSCR_INEXACT 0x00000004 /* Inexact exception */
183 #define SH_FPSCR_UNDERFLOW 0x00000008 /* Underflow exception */
184 #define SH_FPSCR_OVERFLOW 0x00000010 /* Overflow exception */
185 #define SH_FPSCR_DIV_BY_ZERO 0x00000020 /* Div by zero exception */
186 #define SH_FPSCR_INVALID 0x00000040 /* Invalid exception */
187 #define SH_FPSCR_EN_INEXACT 0x00000080 /* Inexact enable */
188 #define SH_FPSCR_EN_UNDERFLOW 0x00000100 /* Underflow enable */
189 #define SH_FPSCR_EN_OVERFLOW 0x00000200 /* Overflow enable */
190 #define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400 /* Div by zero enable */
191 #define SH_FPSCR_EN_INVALID 0x00000800 /* Invalid enable */
192 #define SH_FPSCR_CAUSE_INEXACT 0x00001000 /* Cause Inexact */
193 #define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000 /* Cause Underflow */
194 #define SH_FPSCR_CAUSE_OVERFLOW 0x00004000 /* Cause Overflow */
195 #define SH_FPSCR_CAUSE_DIVBY0 0x00008000 /* Cause Div by 0 */
196 #define SH_FPSCR_CAUSE_INVALID 0x00010000 /* Cause Invalid */
197 #define SH_FPSCR_CAUSE_ERROR 0x00020000 /* Cause Error */
198 #define SH_FPSCR_DN_ZERO 0x00040000 /* Denormalization Mode */
199 #define SH_FPSCR_PR 0x00080000 /* Double-Precision Mode */
200 #define SH_FPSCR_SZ 0x00100000 /* Double-Precision Size */
201 #define SH_FPSCR_FR 0x00200000 /* Register Bank Select */
202
203
204 /* cpu_sh.c: */
205 void sh_cpu_interrupt_assert(struct interrupt *interrupt);
206 void sh_cpu_interrupt_deassert(struct interrupt *interrupt);
207 int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
208 int sh_run_instr(struct cpu *cpu);
209 void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
210 unsigned char *host_page, int writeflag, uint64_t paddr_page);
211 void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
212 void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
213 int sh32_run_instr(struct cpu *cpu);
214 void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
215 unsigned char *host_page, int writeflag, uint64_t paddr_page);
216 void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
217 void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
218 void sh_init_64bit_dummy_tables(struct cpu *cpu);
219 int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
220 unsigned char *data, size_t len, int writeflag, int cache_flags);
221 int sh_cpu_family_init(struct cpu_family *);
222
223 void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
224 void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr);
225
226 /* memory_sh.c: */
227 int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
228 uint64_t *return_addr, int flags);
229
230
231 #endif /* CPU_SH_H */
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