src/include/cpu_sh.h

#ifndef CPU_SH_H
#define CPU_SH_H

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_sh.h,v 1.10 2005/11/16 21:15:19 debug Exp $
 */

#include "misc.h"


struct cpu_family;


#define SH_N_IC_ARGS                    3
#define SH_INSTR_ALIGNMENT_SHIFT        2
#define SH_IC_ENTRIES_SHIFT             10
#define SH_IC_ENTRIES_PER_PAGE          (1 << SH_IC_ENTRIES_SHIFT)
#define SH_PC_TO_IC_ENTRY(a)            (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
                                        & (SH_IC_ENTRIES_PER_PAGE-1))
#define SH_ADDR_TO_PAGENR(a)            ((a) >> (SH_IC_ENTRIES_SHIFT \
                                        + SH_INSTR_ALIGNMENT_SHIFT))

struct sh_instr_call {
        void    (*f)(struct cpu *, struct sh_instr_call *);
        size_t  arg[SH_N_IC_ARGS];
};

/*  Translation cache struct for each physical page:  */
struct sh_tc_physpage {
        struct sh_instr_call ics[SH_IC_ENTRIES_PER_PAGE + 1];
        uint32_t        next_ofs;       /*  or 0 for end of chain  */
        int             flags;
        uint64_t        physaddr;
};

#define SH_N_VPH_ENTRIES                1048576

#define SH_MAX_VPH_TLB_ENTRIES          256
struct sh_vpg_tlb_entry {
        uint8_t         valid;
        uint8_t         writeflag;
        int64_t         timestamp;
        uint64_t        vaddr_page;
        uint64_t        paddr_page;
        unsigned char   *host_page;
};

struct sh_cpu {
        int             bits;
        int             compact;

        uint64_t        r[64];


        /*
         *  Instruction translation cache:
         */

        /*  cur_ic_page is a pointer to an array of SH_IC_ENTRIES_PER_PAGE
            instruction call entries. next_ic points to the next such
            call to be executed.  */
        struct sh_tc_physpage   *cur_physpage;
        struct sh_instr_call    *cur_ic_page;
        struct sh_instr_call    *next_ic;

        void                    (*combination_check)(struct cpu *,
                                    struct sh_instr_call *, int low_addr);

        /*
         *  Virtual -> physical -> host address translation:
         *
         *  host_load and host_store point to arrays of SH_N_VPH_ENTRIES
         *  pointers (to host pages); phys_addr points to an array of
         *  SH_N_VPH_ENTRIES uint32_t.
         */

        struct sh_vpg_tlb_entry  vph_tlb_entry[SH_MAX_VPH_TLB_ENTRIES];
        unsigned char            *host_load[SH_N_VPH_ENTRIES]; 
        unsigned char            *host_store[SH_N_VPH_ENTRIES];
        uint32_t                 phys_addr[SH_N_VPH_ENTRIES]; 
        struct sh_tc_physpage    *phys_page[SH_N_VPH_ENTRIES];

        uint32_t                 phystranslation[SH_N_VPH_ENTRIES/32];
        uint8_t                  vaddr_to_tlbindex[SH_N_VPH_ENTRIES];
};


/*  cpu_sh.c:  */
void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int sh_cpu_family_init(struct cpu_family *);


#endif  /*  CPU_SH_H  */
1	#ifndef CPU_SH_H
2	#define CPU_SH_H
3
4	/*
5	* Copyright (C) 2005 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu_sh.h,v 1.10 2005/11/16 21:15:19 debug Exp $
32	*/
33
34	#include "misc.h"
35
36
37	struct cpu_family;
38
39
40	#define SH_N_IC_ARGS 3
41	#define SH_INSTR_ALIGNMENT_SHIFT 2
42	#define SH_IC_ENTRIES_SHIFT 10
43	#define SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT)
44	#define SH_PC_TO_IC_ENTRY(a) (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
45	& (SH_IC_ENTRIES_PER_PAGE-1))
46	#define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \
47	+ SH_INSTR_ALIGNMENT_SHIFT))
48
49	struct sh_instr_call {
50	void (f)(struct cpu , struct sh_instr_call *);
51	size_t arg[SH_N_IC_ARGS];
52	};
53
54	/* Translation cache struct for each physical page: */
55	struct sh_tc_physpage {
56	struct sh_instr_call ics[SH_IC_ENTRIES_PER_PAGE + 1];
57	uint32_t next_ofs; /* or 0 for end of chain */
58	int flags;
59	uint64_t physaddr;
60	};
61
62	#define SH_N_VPH_ENTRIES 1048576
63
64	#define SH_MAX_VPH_TLB_ENTRIES 256
65	struct sh_vpg_tlb_entry {
66	uint8_t valid;
67	uint8_t writeflag;
68	int64_t timestamp;
69	uint64_t vaddr_page;
70	uint64_t paddr_page;
71	unsigned char *host_page;
72	};
73
74	struct sh_cpu {
75	int bits;
76	int compact;
77
78	uint64_t r[64];
79
80
81	/*
82	* Instruction translation cache:
83	*/
84
85	/* cur_ic_page is a pointer to an array of SH_IC_ENTRIES_PER_PAGE
86	instruction call entries. next_ic points to the next such
87	call to be executed. */
88	struct sh_tc_physpage *cur_physpage;
89	struct sh_instr_call *cur_ic_page;
90	struct sh_instr_call *next_ic;
91
92	void (combination_check)(struct cpu ,
93	struct sh_instr_call *, int low_addr);
94
95	/*
96	* Virtual -> physical -> host address translation:
97	*
98	* host_load and host_store point to arrays of SH_N_VPH_ENTRIES
99	* pointers (to host pages); phys_addr points to an array of
100	* SH_N_VPH_ENTRIES uint32_t.
101	*/
102
103	struct sh_vpg_tlb_entry vph_tlb_entry[SH_MAX_VPH_TLB_ENTRIES];
104	unsigned char *host_load[SH_N_VPH_ENTRIES];
105	unsigned char *host_store[SH_N_VPH_ENTRIES];
106	uint32_t phys_addr[SH_N_VPH_ENTRIES];
107	struct sh_tc_physpage *phys_page[SH_N_VPH_ENTRIES];
108
109	uint32_t phystranslation[SH_N_VPH_ENTRIES/32];
110	uint8_t vaddr_to_tlbindex[SH_N_VPH_ENTRIES];
111	};
112
113
114	/* cpu_sh.c: */
115	void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
116	unsigned char *host_page, int writeflag, uint64_t paddr_page);
117	void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
118	void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
119	void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
120	unsigned char *host_page, int writeflag, uint64_t paddr_page);
121	void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
122	void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
123	int sh_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
124	unsigned char *data, size_t len, int writeflag, int cache_flags);
125	int sh_cpu_family_init(struct cpu_family *);
126
127
128	#endif /* CPU_SH_H */