/[gxemul]/trunk/src/include/cpu_sh.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 14 by dpavlin, Mon Oct 8 16:18:51 2007 UTC revision 44 by dpavlin, Mon Oct 8 16:22:56 2007 UTC
# Line 2  Line 2 
2  #define CPU_SH_H  #define CPU_SH_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_sh.h,v 1.4 2005/09/04 13:06:11 debug Exp $   *  $Id: cpu_sh.h,v 1.50 2007/07/20 09:03:33 debug Exp $
32     *
33     *  Note 1: Many things here are SH4-specific, so it probably doesn't work
34     *          for SH3 emulation.
35     *
36     *  Note 2: The SuperH emulation in GXemul does not include SH5/SH64 at
37     *          this time. There doesn't seem to be that much interesting code
38     *          to run in the emulator for SH5. :-/
39   */   */
40    
41    #include "interrupt.h"
42  #include "misc.h"  #include "misc.h"
43    #include "sh4_cpu.h"
44    
45    
46  struct cpu_family;  struct cpu_family;
47    
48    
49  #define SH_N_IC_ARGS                    3  /*  SH CPU types:  */
50  #define SH_INSTR_ALIGNMENT_SHIFT        2  struct sh_cpu_type_def {
51  #define SH_IC_ENTRIES_SHIFT             10          char            *name;
52            int             bits;
53            int             arch;
54            uint32_t        pvr;
55            uint32_t        prr;
56    };
57    
58    #define SH_CPU_TYPE_DEFS                                {           \
59            { "SH7708R", 32, 3, 0,              0,                   }, \
60            { "SH7750",  32, 4, SH4_PVR_SH7750, 0                    }, \
61            { "SH7750R", 32, 4, SH4_PVR_SH7750, SH4_PRR_7750R        }, \
62            { "SH7751R", 32, 4, SH4_PVR_SH7751, SH4_PRR_7751R        }, \
63            /* { "SH5",  64, 5, 0,              0                    }, */ \
64            { NULL,       0, 0, 0,              0                    }  }
65    
66    
67    #define SH_N_IC_ARGS                    2
68    #define SH_INSTR_ALIGNMENT_SHIFT        1
69    #define SH_IC_ENTRIES_SHIFT             11
70  #define SH_IC_ENTRIES_PER_PAGE          (1 << SH_IC_ENTRIES_SHIFT)  #define SH_IC_ENTRIES_PER_PAGE          (1 << SH_IC_ENTRIES_SHIFT)
71  #define SH_PC_TO_IC_ENTRY(a)            (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \  #define SH_PC_TO_IC_ENTRY(a)            (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
72                                          & (SH_IC_ENTRIES_PER_PAGE-1))                                          & (SH_IC_ENTRIES_PER_PAGE-1))
73  #define SH_ADDR_TO_PAGENR(a)            ((a) >> (SH_IC_ENTRIES_SHIFT \  #define SH_ADDR_TO_PAGENR(a)            ((a) >> (SH_IC_ENTRIES_SHIFT \
74                                          + SH_INSTR_ALIGNMENT_SHIFT))                                          + SH_INSTR_ALIGNMENT_SHIFT))
75    
76  struct sh_instr_call {  DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_t)
         void    (*f)(struct cpu *, struct sh_instr_call *);  
         size_t  arg[SH_N_IC_ARGS];  
 };  
77    
78  /*  Translation cache struct for each physical page:  */  #define SH_MAX_VPH_TLB_ENTRIES          128
 struct sh_tc_physpage {  
         uint32_t        next_ofs;       /*  or 0 for end of chain  */  
         uint64_t        physaddr;  
         int             flags;  
         struct sh_instr_call ics[SH_IC_ENTRIES_PER_PAGE + 1];  
 };  
79    
 #define SH_N_VPH_ENTRIES                1048576  
80    
81  #define SH_MAX_VPH_TLB_ENTRIES          256  #define SH_N_GPRS               16
82  struct sh_vpg_tlb_entry {  #define SH_N_GPRS_BANKED        8
83          int             valid;  #define SH_N_FPRS               16
         int             writeflag;  
         int64_t         timestamp;  
         unsigned char   *host_page;  
         uint64_t        vaddr_page;  
         uint64_t        paddr_page;  
 };  
84    
85  struct sh_cpu {  #define SH_N_ITLB_ENTRIES       4
86          int             bits;  #define SH_N_UTLB_ENTRIES       64
         int             compact;  
87    
88          uint64_t        r[64];  /*  An instruction with an invalid encoding; used for software
89        emulation of PROM calls within GXemul:  */
90    #define SH_INVALID_INSTR        0x00fb
91    
92    
93          /*  struct sh_cpu {
94           *  Instruction translation cache:          struct sh_cpu_type_def cpu_type;
          */  
95    
96          /*  cur_ic_page is a pointer to an array of SH_IC_ENTRIES_PER_PAGE          /*  General Purpose Registers:  */
97              instruction call entries. next_ic points to the next such          uint32_t        r[SH_N_GPRS];
98              call to be executed.  */          uint32_t        r_bank[SH_N_GPRS_BANKED];
99          struct sh_tc_physpage   *cur_physpage;  
100          struct sh_instr_call    *cur_ic_page;          /*  Floating-Point Registers:  */
101          struct sh_instr_call    *next_ic;          uint32_t        fr[SH_N_FPRS];
102            uint32_t        xf[SH_N_FPRS];  /*  "Other bank."  */
103    
104            uint32_t        mach;           /*  Multiply-Accumulate High  */
105            uint32_t        macl;           /*  Multiply-Accumulate Low  */
106            uint32_t        pr;             /*  Procedure Register  */
107            uint32_t        fpscr;          /*  Floating-point Status/Control  */
108            uint32_t        fpul;           /*  Floating-point Communication Reg  */
109            uint32_t        sr;             /*  Status Register  */
110            uint32_t        ssr;            /*  Saved Status Register  */
111            uint32_t        spc;            /*  Saved PC  */
112            uint32_t        gbr;            /*  Global Base Register  */
113            uint32_t        vbr;            /*  Vector Base Register  */
114            uint32_t        sgr;            /*  Saved General Register  */
115            uint32_t        dbr;            /*  Debug Base Register  */
116    
117            /*  Cache control:  */
118            uint32_t        ccr;            /*  Cache Control Register  */
119            uint32_t        qacr0;          /*  Queue Address Control Register 0  */
120            uint32_t        qacr1;          /*  Queue Address Control Register 1  */
121    
122            /*  MMU/TLB registers:  */
123            uint32_t        pteh;           /*  Page Table Entry High  */
124            uint32_t        ptel;           /*  Page Table Entry Low  */
125            uint32_t        ptea;           /*  Page Table Entry A  */
126            uint32_t        ttb;            /*  Translation Table Base  */
127            uint32_t        tea;            /*  TLB Exception Address Register  */
128            uint32_t        mmucr;          /*  MMU Control Register  */
129            uint32_t        itlb_hi[SH_N_ITLB_ENTRIES];
130            uint32_t        itlb_lo[SH_N_ITLB_ENTRIES];
131            uint32_t        utlb_hi[SH_N_UTLB_ENTRIES];
132            uint32_t        utlb_lo[SH_N_UTLB_ENTRIES];
133    
134            /*  Exception handling:  */
135            uint32_t        tra;            /*  TRAPA Exception Register  */
136            uint32_t        expevt;         /*  Exception Event Register  */
137            uint32_t        intevt;         /*  Interrupt Event Register  */
138    
139            /*  Interrupt controller:  */
140            uint16_t        intc_ipra;      /*  Interrupt Priority Registers  */
141            uint16_t        intc_iprb;
142            uint16_t        intc_iprc;
143            uint16_t        intc_iprd;
144            uint32_t        intc_intpri00;
145            uint32_t        intc_intpri04;
146            uint32_t        intc_intpri08;
147            uint32_t        intc_intpri0c;
148            uint32_t        intc_intreq00;
149            uint32_t        intc_intreq04;
150            uint32_t        intc_intmsk00;
151            uint32_t        intc_intmsk04;
152            /*  Cached and calculated values:  */
153            uint8_t         int_prio_and_pending[0x1000 / 0x20];
154            int16_t         int_to_assert;  /*  Calculated int to assert  */
155            unsigned int    int_level;      /*  Calculated int level  */
156    
157            /*  Timer/clock functionality:  */
158            int             pclock;
159    
160            /*  DMA Controller: (4 channels)  */
161            uint32_t        dmac_sar[4];
162            uint32_t        dmac_dar[4];
163            uint32_t        dmac_tcr[4];
164            uint32_t        dmac_chcr[4];
165    
166            /*  PCI controller:  */
167            struct pci_data *pcic_pcibus;
168    
169    
170          /*          /*
171           *  Virtual -> physical -> host address translation:           *  Instruction translation cache and Virtual->Physical->Host
172           *           *  address translation:
          *  host_load and host_store point to arrays of SH_N_VPH_ENTRIES  
          *  pointers (to host pages); phys_addr points to an array of  
          *  SH_N_VPH_ENTRIES uint32_t.  
173           */           */
174            DYNTRANS_ITC(sh)
175          struct sh_vpg_tlb_entry  vph_tlb_entry[SH_MAX_VPH_TLB_ENTRIES];          VPH_TLBS(sh,SH)
176          unsigned char               *host_load[SH_N_VPH_ENTRIES];          VPH32(sh,SH)
         unsigned char               *host_store[SH_N_VPH_ENTRIES];  
         uint32_t                    phys_addr[SH_N_VPH_ENTRIES];  
         struct sh_tc_physpage    *phys_page[SH_N_VPH_ENTRIES];  
177  };  };
178    
179    
180    /*  Status register bits:  */
181    #define SH_SR_T                 0x00000001      /*  True/false  */
182    #define SH_SR_S                 0x00000002      /*  Saturation  */
183    #define SH_SR_IMASK             0x000000f0      /*  Interrupt mask  */
184    #define SH_SR_IMASK_SHIFT               4
185    #define SH_SR_Q                 0x00000100      /*  State for Divide Step  */
186    #define SH_SR_M                 0x00000200      /*  State for Divide Step  */
187    #define SH_SR_FD                0x00008000      /*  FPU Disable  */
188    #define SH_SR_BL                0x10000000      /*  Exception/Interrupt Block */
189    #define SH_SR_RB                0x20000000      /*  Register Bank 0/1  */
190    #define SH_SR_MD                0x40000000      /*  Privileged Mode  */
191    
192    /*  Floating-point status/control register bits:  */
193    #define SH_FPSCR_RM_MASK        0x00000003      /*  Rounding Mode  */
194    #define    SH_FPSCR_RM_NEAREST         0x0      /*  Round to nearest  */
195    #define    SH_FPSCR_RM_ZERO            0x1      /*  Round to zero  */
196    #define SH_FPSCR_INEXACT        0x00000004      /*  Inexact exception  */
197    #define SH_FPSCR_UNDERFLOW      0x00000008      /*  Underflow exception  */
198    #define SH_FPSCR_OVERFLOW       0x00000010      /*  Overflow exception  */
199    #define SH_FPSCR_DIV_BY_ZERO    0x00000020      /*  Div by zero exception  */
200    #define SH_FPSCR_INVALID        0x00000040      /*  Invalid exception  */
201    #define SH_FPSCR_EN_INEXACT     0x00000080      /*  Inexact enable  */
202    #define SH_FPSCR_EN_UNDERFLOW   0x00000100      /*  Underflow enable  */
203    #define SH_FPSCR_EN_OVERFLOW    0x00000200      /*  Overflow enable  */
204    #define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400      /*  Div by zero enable  */
205    #define SH_FPSCR_EN_INVALID     0x00000800      /*  Invalid enable  */
206    #define SH_FPSCR_CAUSE_INEXACT  0x00001000      /*  Cause Inexact  */
207    #define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000     /*  Cause Underflow  */
208    #define SH_FPSCR_CAUSE_OVERFLOW 0x00004000      /*  Cause Overflow  */
209    #define SH_FPSCR_CAUSE_DIVBY0   0x00008000      /*  Cause Div by 0  */
210    #define SH_FPSCR_CAUSE_INVALID  0x00010000      /*  Cause Invalid  */
211    #define SH_FPSCR_CAUSE_ERROR    0x00020000      /*  Cause Error  */
212    #define SH_FPSCR_DN_ZERO        0x00040000      /*  Denormalization Mode  */
213    #define SH_FPSCR_PR             0x00080000      /*  Double-Precision Mode  */
214    #define SH_FPSCR_SZ             0x00100000      /*  Double-Precision Size  */
215    #define SH_FPSCR_FR             0x00200000      /*  Register Bank Select  */
216    
217    
218    /*  int_prio_and_pending bits:  */
219    #define SH_INT_ASSERTED         0x10
220    #define SH_INT_PRIO_MASK        0x0f
221    
222  /*  cpu_sh.c:  */  /*  cpu_sh.c:  */
223    void sh_cpu_interrupt_assert(struct interrupt *interrupt);
224    void sh_cpu_interrupt_deassert(struct interrupt *interrupt);
225    int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
226    int sh_run_instr(struct cpu *cpu);
227  void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
228          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
229  void sh_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);  void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
230  void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
231  void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sh_init_64bit_dummy_tables(struct cpu *cpu);
         unsigned char *host_page, int writeflag, uint64_t paddr_page);  
 void sh32_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);  
 void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  
232  int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
233          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
234  int sh_cpu_family_init(struct cpu_family *);  int sh_cpu_family_init(struct cpu_family *);
235    
236    void sh_update_interrupt_priorities(struct cpu *cpu);
237    void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
238    void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr);
239    
240    /*  memory_sh.c:  */
241    int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
242            uint64_t *return_addr, int flags);
243    
244    
245  #endif  /*  CPU_SH_H  */  #endif  /*  CPU_SH_H  */
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