/[gxemul]/trunk/src/include/cpu_sh.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 32 by dpavlin, Mon Oct 8 16:20:58 2007 UTC revision 36 by dpavlin, Mon Oct 8 16:21:34 2007 UTC
# Line 2  Line 2 
2  #define CPU_SH_H  #define CPU_SH_H
3    
4  /*  /*
5   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_sh.h,v 1.33 2006/10/27 15:51:37 debug Exp $   *  $Id: cpu_sh.h,v 1.38 2007/02/24 19:21:44 debug Exp $
32   *   *
33   *  Note: Many things here are SH4-specific, so it probably doesn't work   *  Note: Many things here are SH4-specific, so it probably doesn't work
34   *        for SH3 emulation.   *        for SH3 emulation.
35   */   */
36    
37    #include "interrupt.h"
38  #include "misc.h"  #include "misc.h"
39  #include "sh4_cpu.h"  #include "sh4_cpu.h"
40    
# Line 49  struct sh_cpu_type_def { Line 50  struct sh_cpu_type_def {
50          uint32_t        prr;          uint32_t        prr;
51  };  };
52    
53  #define SH_CPU_TYPE_DEFS                {           \  #define SH_CPU_TYPE_DEFS                                {           \
54          { "SH7750", 32, 4, SH4_PVR_SH7750, 0     }, \          { "SH7750",  32, 4, SH4_PVR_SH7750, 0                    }, \
55          { "SH5",    64, 5, 0,              0     }, \          { "SH7750R", 32, 4, SH4_PVR_SH7750, SH4_PRR_7750R        }, \
56          { NULL,      0, 0, 0,              0     }  }          { "SH7751R", 32, 4, SH4_PVR_SH7751, SH4_PRR_7751R        }, \
57            { "SH5",     64, 5, 0,              0                    }, \
58            { NULL,       0, 0, 0,              0                    }  }
59    
60    
61  /*  /*
# Line 81  DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_ Line 84  DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_
84  #define SH_N_ITLB_ENTRIES       4  #define SH_N_ITLB_ENTRIES       4
85  #define SH_N_UTLB_ENTRIES       64  #define SH_N_UTLB_ENTRIES       64
86    
87    #define SH_INVALID_INSTR        0x00fb
88    
89    
90  struct sh_cpu {  struct sh_cpu {
91          struct sh_cpu_type_def cpu_type;          struct sh_cpu_type_def cpu_type;
# Line 135  struct sh_cpu { Line 140  struct sh_cpu {
140          uint16_t        intc_ipra;      /*  Interrupt Priority Registers  */          uint16_t        intc_ipra;      /*  Interrupt Priority Registers  */
141          uint16_t        intc_iprb;          uint16_t        intc_iprb;
142          uint16_t        intc_iprc;          uint16_t        intc_iprc;
143            uint16_t        intc_iprd;
144          int16_t         int_to_assert;  /*  Calculated int to assert  */          int16_t         int_to_assert;  /*  Calculated int to assert  */
145          int             int_level;      /*  Calculated int level  */          int             int_level;      /*  Calculated int level  */
146          uint32_t        int_pending[0x1000 / 0x20 / (sizeof(uint32_t)*8)];          uint32_t        int_pending[0x1000 / 0x20 / (sizeof(uint32_t)*8)];
# Line 142  struct sh_cpu { Line 148  struct sh_cpu {
148          /*  Timer/clock functionality:  */          /*  Timer/clock functionality:  */
149          int             pclock;          int             pclock;
150    
151            /*  DMA Controller: (4 channels)  */
152            uint32_t        dmac_sar[4];
153            uint32_t        dmac_dar[4];
154            uint32_t        dmac_tcr[4];
155            uint32_t        dmac_chcr[4];
156    
157    
158          /*          /*
159           *  Instruction translation cache and Virtual->Physical->Host           *  Instruction translation cache and Virtual->Physical->Host
# Line 192  struct sh_cpu { Line 204  struct sh_cpu {
204    
205    
206  /*  cpu_sh.c:  */  /*  cpu_sh.c:  */
207    void sh_cpu_interrupt_assert(struct interrupt *interrupt);
208    void sh_cpu_interrupt_deassert(struct interrupt *interrupt);
209  int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);  int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
210  int sh_run_instr(struct cpu *cpu);  int sh_run_instr(struct cpu *cpu);
211  void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
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