--- trunk/src/include/cpu_sh.h	2007/10/08 16:20:40	30
+++ trunk/src/include/cpu_sh.h	2007/10/08 16:20:58	32
@@ -28,10 +28,14 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_sh.h,v 1.21 2006/07/25 21:49:14 debug Exp $
+ *  $Id: cpu_sh.h,v 1.33 2006/10/27 15:51:37 debug Exp $
+ *
+ *  Note: Many things here are SH4-specific, so it probably doesn't work
+ *        for SH3 emulation.
  */
 
 #include "misc.h"
+#include "sh4_cpu.h"
 
 
 struct cpu_family;
@@ -40,13 +44,15 @@
 struct sh_cpu_type_def {
 	char		*name;
 	int		bits;
+	int		arch;
+	uint32_t	pvr;
+	uint32_t	prr;
 };
 
-#define	SH_CPU_TYPE_DEFS	{	\
-	{ "SH3", 32 },			\
-	{ "SH4", 32 },			\
-	{ "SH5", 64 },			\
-	{ NULL, 0 } }
+#define	SH_CPU_TYPE_DEFS		{	    \
+	{ "SH7750", 32, 4, SH4_PVR_SH7750, 0	 }, \
+	{ "SH5",    64, 5, 0,              0	 }, \
+	{ NULL,      0, 0, 0,              0	 }  }
 
 
 /*
@@ -63,16 +69,17 @@
 #define	SH_ADDR_TO_PAGENR(a)		((a) >> (SH_IC_ENTRIES_SHIFT \
 					+ SH_INSTR_ALIGNMENT_SHIFT))
 
-#define	SH_L2N		17
-#define	SH_L3N		18
-
-DYNTRANS_MISC_DECLARATIONS(sh,SH,uint64_t)
-DYNTRANS_MISC64_DECLARATIONS(sh,SH,uint8_t)
+DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_t)
 
 #define	SH_MAX_VPH_TLB_ENTRIES		128
 
 
-#define	SH_N_GPRS		64
+#define	SH_N_GPRS		16
+#define	SH_N_GPRS_BANKED	8
+#define	SH_N_FPRS		16
+
+#define	SH_N_ITLB_ENTRIES	4
+#define	SH_N_UTLB_ENTRIES	64
 
 
 struct sh_cpu {
@@ -81,9 +88,13 @@
 	/*  compact = 1 if currently executing 16-bit long opcodes  */
 	int		compact;
 
-	uint32_t	r_otherbank[8];
-
-	uint64_t	r[SH_N_GPRS];
+	/*  General Purpose Registers:  */
+	uint32_t	r[SH_N_GPRS];
+	uint32_t	r_bank[SH_N_GPRS_BANKED];
+
+	/*  Floating-Point Registers:  */
+	uint32_t	fr[SH_N_FPRS];
+	uint32_t	xf[SH_N_FPRS];	/*  "Other bank."  */
 
 	uint32_t	mach;		/*  Multiply-Accumulate High  */
 	uint32_t	macl;		/*  Multiply-Accumulate Low  */
@@ -98,6 +109,39 @@
 	uint32_t	sgr;		/*  Saved General Register  */
 	uint32_t	dbr;		/*  Debug Base Register  */
 
+	/*  Cache control:  */
+	uint32_t	ccr;		/*  Cache Control Register  */
+	uint32_t	qacr0;		/*  Queue Address Control Register 0  */
+	uint32_t	qacr1;		/*  Queue Address Control Register 1  */
+
+	/*  MMU/TLB registers:  */
+	uint32_t	pteh;		/*  Page Table Entry High  */
+	uint32_t	ptel;		/*  Page Table Entry Low  */
+	uint32_t	ptea;		/*  Page Table Entry A  */
+	uint32_t	ttb;		/*  Translation Table Base  */
+	uint32_t	tea;		/*  TLB Exception Address Register  */
+	uint32_t	mmucr;		/*  MMU Control Register  */
+	uint32_t	itlb_hi[SH_N_ITLB_ENTRIES];
+	uint32_t	itlb_lo[SH_N_ITLB_ENTRIES];
+	uint32_t	utlb_hi[SH_N_UTLB_ENTRIES];
+	uint32_t	utlb_lo[SH_N_UTLB_ENTRIES];
+
+	/*  Exception handling:  */
+	uint32_t	tra;		/*  TRAPA Exception Register  */
+	uint32_t	expevt;		/*  Exception Event Register  */
+	uint32_t	intevt;		/*  Interrupt Event Register  */
+
+	/*  Interrupt controller:  */
+	uint16_t	intc_ipra;	/*  Interrupt Priority Registers  */
+	uint16_t	intc_iprb;
+	uint16_t	intc_iprc;
+	int16_t		int_to_assert;	/*  Calculated int to assert  */
+	int		int_level;	/*  Calculated int level  */
+	uint32_t	int_pending[0x1000 / 0x20 / (sizeof(uint32_t)*8)];
+
+	/*  Timer/clock functionality:  */
+	int		pclock;
+
 
 	/*
 	 *  Instruction translation cache and Virtual->Physical->Host
@@ -106,7 +150,6 @@
 	DYNTRANS_ITC(sh)
 	VPH_TLBS(sh,SH)
 	VPH32(sh,SH,uint64_t,uint8_t)
-	VPH64(sh,SH,uint8_t)
 };
 
 
@@ -122,8 +165,34 @@
 #define	SH_SR_RB		0x20000000	/*  Register Bank 0/1  */
 #define	SH_SR_MD		0x40000000	/*  Privileged Mode  */
 
+/*  Floating-point status/control register bits:  */
+#define	SH_FPSCR_RM_MASK	0x00000003	/*  Rounding Mode  */
+#define	   SH_FPSCR_RM_NEAREST	       0x0	/*  Round to nearest  */
+#define	   SH_FPSCR_RM_ZERO	       0x1	/*  Round to zero  */
+#define	SH_FPSCR_INEXACT	0x00000004	/*  Inexact exception  */
+#define	SH_FPSCR_UNDERFLOW	0x00000008	/*  Underflow exception  */
+#define	SH_FPSCR_OVERFLOW	0x00000010	/*  Overflow exception  */
+#define	SH_FPSCR_DIV_BY_ZERO	0x00000020	/*  Div by zero exception  */
+#define	SH_FPSCR_INVALID	0x00000040	/*  Invalid exception  */
+#define	SH_FPSCR_EN_INEXACT	0x00000080	/*  Inexact enable  */
+#define	SH_FPSCR_EN_UNDERFLOW	0x00000100	/*  Underflow enable  */
+#define	SH_FPSCR_EN_OVERFLOW	0x00000200	/*  Overflow enable  */
+#define	SH_FPSCR_EN_DIV_BY_ZERO	0x00000400	/*  Div by zero enable  */
+#define	SH_FPSCR_EN_INVALID	0x00000800	/*  Invalid enable  */
+#define	SH_FPSCR_CAUSE_INEXACT	0x00001000	/*  Cause Inexact  */
+#define	SH_FPSCR_CAUSE_UNDERFLOW 0x00002000	/*  Cause Underflow  */
+#define	SH_FPSCR_CAUSE_OVERFLOW	0x00004000	/*  Cause Overflow  */
+#define	SH_FPSCR_CAUSE_DIVBY0	0x00008000	/*  Cause Div by 0  */
+#define	SH_FPSCR_CAUSE_INVALID	0x00010000	/*  Cause Invalid  */
+#define	SH_FPSCR_CAUSE_ERROR	0x00020000	/*  Cause Error  */
+#define	SH_FPSCR_DN_ZERO	0x00040000	/*  Denormalization Mode  */
+#define	SH_FPSCR_PR		0x00080000	/*  Double-Precision Mode  */
+#define	SH_FPSCR_SZ		0x00100000	/*  Double-Precision Size  */
+#define	SH_FPSCR_FR		0x00200000	/*  Register Bank Select  */
+
 
 /*  cpu_sh.c:  */
+int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
 int sh_run_instr(struct cpu *cpu);
 void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
 	unsigned char *host_page, int writeflag, uint64_t paddr_page);
@@ -140,6 +209,7 @@
 int sh_cpu_family_init(struct cpu_family *);
 
 void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
+void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr);
 
 /*  memory_sh.c:  */
 int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,