28 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
29 |
* |
* |
30 |
* |
* |
31 |
* $Id: cpu_sh.h,v 1.37 2006/12/30 13:31:00 debug Exp $ |
* $Id: cpu_sh.h,v 1.38 2007/02/24 19:21:44 debug Exp $ |
32 |
* |
* |
33 |
* Note: Many things here are SH4-specific, so it probably doesn't work |
* Note: Many things here are SH4-specific, so it probably doesn't work |
34 |
* for SH3 emulation. |
* for SH3 emulation. |
50 |
uint32_t prr; |
uint32_t prr; |
51 |
}; |
}; |
52 |
|
|
53 |
#define SH_CPU_TYPE_DEFS { \ |
#define SH_CPU_TYPE_DEFS { \ |
54 |
{ "SH7750", 32, 4, SH4_PVR_SH7750, 0 }, \ |
{ "SH7750", 32, 4, SH4_PVR_SH7750, 0 }, \ |
55 |
{ "SH5", 64, 5, 0, 0 }, \ |
{ "SH7750R", 32, 4, SH4_PVR_SH7750, SH4_PRR_7750R }, \ |
56 |
{ NULL, 0, 0, 0, 0 } } |
{ "SH7751R", 32, 4, SH4_PVR_SH7751, SH4_PRR_7751R }, \ |
57 |
|
{ "SH5", 64, 5, 0, 0 }, \ |
58 |
|
{ NULL, 0, 0, 0, 0 } } |
59 |
|
|
60 |
|
|
61 |
/* |
/* |