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#define CPU_SH_H |
#define CPU_SH_H |
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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_sh.h,v 1.21 2006/07/25 21:49:14 debug Exp $ |
* $Id: cpu_sh.h,v 1.37 2006/12/30 13:31:00 debug Exp $ |
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* |
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* Note: Many things here are SH4-specific, so it probably doesn't work |
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* for SH3 emulation. |
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*/ |
*/ |
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#include "interrupt.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "sh4_cpu.h" |
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struct cpu_family; |
struct cpu_family; |
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struct sh_cpu_type_def { |
struct sh_cpu_type_def { |
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char *name; |
char *name; |
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int bits; |
int bits; |
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int arch; |
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uint32_t pvr; |
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uint32_t prr; |
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}; |
}; |
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#define SH_CPU_TYPE_DEFS { \ |
#define SH_CPU_TYPE_DEFS { \ |
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{ "SH3", 32 }, \ |
{ "SH7750", 32, 4, SH4_PVR_SH7750, 0 }, \ |
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{ "SH4", 32 }, \ |
{ "SH5", 64, 5, 0, 0 }, \ |
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{ "SH5", 64 }, \ |
{ NULL, 0, 0, 0, 0 } } |
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{ NULL, 0 } } |
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/* |
/* |
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#define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \ |
#define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \ |
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+ SH_INSTR_ALIGNMENT_SHIFT)) |
+ SH_INSTR_ALIGNMENT_SHIFT)) |
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#define SH_L2N 17 |
DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_t) |
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#define SH_L3N 18 |
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DYNTRANS_MISC_DECLARATIONS(sh,SH,uint64_t) |
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DYNTRANS_MISC64_DECLARATIONS(sh,SH,uint8_t) |
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#define SH_MAX_VPH_TLB_ENTRIES 128 |
#define SH_MAX_VPH_TLB_ENTRIES 128 |
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#define SH_N_GPRS 64 |
#define SH_N_GPRS 16 |
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#define SH_N_GPRS_BANKED 8 |
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#define SH_N_FPRS 16 |
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#define SH_N_ITLB_ENTRIES 4 |
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#define SH_N_UTLB_ENTRIES 64 |
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#define SH_INVALID_INSTR 0x00fb |
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struct sh_cpu { |
struct sh_cpu { |
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/* compact = 1 if currently executing 16-bit long opcodes */ |
/* compact = 1 if currently executing 16-bit long opcodes */ |
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int compact; |
int compact; |
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uint32_t r_otherbank[8]; |
/* General Purpose Registers: */ |
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uint32_t r[SH_N_GPRS]; |
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uint64_t r[SH_N_GPRS]; |
uint32_t r_bank[SH_N_GPRS_BANKED]; |
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/* Floating-Point Registers: */ |
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uint32_t fr[SH_N_FPRS]; |
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uint32_t xf[SH_N_FPRS]; /* "Other bank." */ |
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uint32_t mach; /* Multiply-Accumulate High */ |
uint32_t mach; /* Multiply-Accumulate High */ |
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uint32_t macl; /* Multiply-Accumulate Low */ |
uint32_t macl; /* Multiply-Accumulate Low */ |
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uint32_t sgr; /* Saved General Register */ |
uint32_t sgr; /* Saved General Register */ |
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uint32_t dbr; /* Debug Base Register */ |
uint32_t dbr; /* Debug Base Register */ |
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/* Cache control: */ |
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uint32_t ccr; /* Cache Control Register */ |
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uint32_t qacr0; /* Queue Address Control Register 0 */ |
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uint32_t qacr1; /* Queue Address Control Register 1 */ |
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/* MMU/TLB registers: */ |
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uint32_t pteh; /* Page Table Entry High */ |
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uint32_t ptel; /* Page Table Entry Low */ |
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uint32_t ptea; /* Page Table Entry A */ |
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uint32_t ttb; /* Translation Table Base */ |
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uint32_t tea; /* TLB Exception Address Register */ |
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uint32_t mmucr; /* MMU Control Register */ |
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uint32_t itlb_hi[SH_N_ITLB_ENTRIES]; |
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uint32_t itlb_lo[SH_N_ITLB_ENTRIES]; |
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uint32_t utlb_hi[SH_N_UTLB_ENTRIES]; |
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uint32_t utlb_lo[SH_N_UTLB_ENTRIES]; |
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/* Exception handling: */ |
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uint32_t tra; /* TRAPA Exception Register */ |
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uint32_t expevt; /* Exception Event Register */ |
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uint32_t intevt; /* Interrupt Event Register */ |
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/* Interrupt controller: */ |
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uint16_t intc_ipra; /* Interrupt Priority Registers */ |
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uint16_t intc_iprb; |
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uint16_t intc_iprc; |
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uint16_t intc_iprd; |
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int16_t int_to_assert; /* Calculated int to assert */ |
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int int_level; /* Calculated int level */ |
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uint32_t int_pending[0x1000 / 0x20 / (sizeof(uint32_t)*8)]; |
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/* Timer/clock functionality: */ |
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int pclock; |
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/* DMA Controller: (4 channels) */ |
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uint32_t dmac_sar[4]; |
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uint32_t dmac_dar[4]; |
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uint32_t dmac_tcr[4]; |
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uint32_t dmac_chcr[4]; |
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/* |
/* |
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* Instruction translation cache and Virtual->Physical->Host |
* Instruction translation cache and Virtual->Physical->Host |
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DYNTRANS_ITC(sh) |
DYNTRANS_ITC(sh) |
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VPH_TLBS(sh,SH) |
VPH_TLBS(sh,SH) |
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VPH32(sh,SH,uint64_t,uint8_t) |
VPH32(sh,SH,uint64_t,uint8_t) |
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VPH64(sh,SH,uint8_t) |
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}; |
}; |
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#define SH_SR_RB 0x20000000 /* Register Bank 0/1 */ |
#define SH_SR_RB 0x20000000 /* Register Bank 0/1 */ |
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#define SH_SR_MD 0x40000000 /* Privileged Mode */ |
#define SH_SR_MD 0x40000000 /* Privileged Mode */ |
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/* Floating-point status/control register bits: */ |
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#define SH_FPSCR_RM_MASK 0x00000003 /* Rounding Mode */ |
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#define SH_FPSCR_RM_NEAREST 0x0 /* Round to nearest */ |
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#define SH_FPSCR_RM_ZERO 0x1 /* Round to zero */ |
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#define SH_FPSCR_INEXACT 0x00000004 /* Inexact exception */ |
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#define SH_FPSCR_UNDERFLOW 0x00000008 /* Underflow exception */ |
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#define SH_FPSCR_OVERFLOW 0x00000010 /* Overflow exception */ |
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#define SH_FPSCR_DIV_BY_ZERO 0x00000020 /* Div by zero exception */ |
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#define SH_FPSCR_INVALID 0x00000040 /* Invalid exception */ |
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#define SH_FPSCR_EN_INEXACT 0x00000080 /* Inexact enable */ |
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#define SH_FPSCR_EN_UNDERFLOW 0x00000100 /* Underflow enable */ |
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#define SH_FPSCR_EN_OVERFLOW 0x00000200 /* Overflow enable */ |
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#define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400 /* Div by zero enable */ |
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#define SH_FPSCR_EN_INVALID 0x00000800 /* Invalid enable */ |
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#define SH_FPSCR_CAUSE_INEXACT 0x00001000 /* Cause Inexact */ |
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#define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000 /* Cause Underflow */ |
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#define SH_FPSCR_CAUSE_OVERFLOW 0x00004000 /* Cause Overflow */ |
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#define SH_FPSCR_CAUSE_DIVBY0 0x00008000 /* Cause Div by 0 */ |
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#define SH_FPSCR_CAUSE_INVALID 0x00010000 /* Cause Invalid */ |
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#define SH_FPSCR_CAUSE_ERROR 0x00020000 /* Cause Error */ |
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#define SH_FPSCR_DN_ZERO 0x00040000 /* Denormalization Mode */ |
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#define SH_FPSCR_PR 0x00080000 /* Double-Precision Mode */ |
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#define SH_FPSCR_SZ 0x00100000 /* Double-Precision Size */ |
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#define SH_FPSCR_FR 0x00200000 /* Register Bank Select */ |
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/* cpu_sh.c: */ |
/* cpu_sh.c: */ |
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void sh_cpu_interrupt_assert(struct interrupt *interrupt); |
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void sh_cpu_interrupt_deassert(struct interrupt *interrupt); |
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int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
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int sh_run_instr(struct cpu *cpu); |
int sh_run_instr(struct cpu *cpu); |
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void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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int sh_cpu_family_init(struct cpu_family *); |
int sh_cpu_family_init(struct cpu_family *); |
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void sh_update_sr(struct cpu *cpu, uint32_t new_sr); |
void sh_update_sr(struct cpu *cpu, uint32_t new_sr); |
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void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr); |
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/* memory_sh.c: */ |
/* memory_sh.c: */ |
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int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr, |
int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr, |